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An architecture for the scalable speed and multiple supply voltage range of 1.6 V to 3.6 V, low voltage to high voltage level shifter has been proposed. The buffer containing the level shifter is fabricated in 40 nm CMOS process by thin oxide (32Å thick) devices whose stress limit is 1.98 V (max). The technique generates a set of dynamic differential bias signals as a function of input data sequence, output state of the level shifter and the supply voltage for a given process and temperature to ensure the reliable operation of the level shift stage. The measurement results confirmed successful operation at 40 Mbps with 10 pF load on IO pad, with multiple supplies, 1.8 V -2.7 V -3.6 V.

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I. ABSTRACTA multi-gigabit inductor-less wide-range adaptive continuous time equalizer (CTE) architecture is presented. The incoming data stream is equalized using one-bit post-cursor clock-less dynamic feedback. The circuit adapts to a given link environment (noisy channel and the termination) by controlling the amount of feedback and thereby defining the high-frequency and low-frequency response. The architecture is scalable to higher speeds with technology. The circuit can be operated in different modes based on the attenuation in the input signal at a given operating frequency. Measurement results depict the successful equalization of channels having an attenuation of upto −19 dB at 10 GHz. The circuit is fabricated in 0.13 μm CMOS technology and consumes a current of 39 mA (max.) at (V dd = 1.32 V ) in the low power mode.