A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique

Nazir, Liyaqat; Khurshid, Burhan; Mir, Roohie Naaz

doi:10.1109/indicon.2015.7443459

Cited by 8 publications

(4 citation statements)

References 13 publications

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“…In full adder based encoder we are using ADC with transmission gate and opamps to reduce the delay and power [2]. In flash ADC using opamps to make the power low and also to reduce the delay we are using as shown in the figure 5.…”

Section: B Full Adder Based Encodermentioning

confidence: 99%

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TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019

ijrte

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Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

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Section: B Full Adder Based Encodermentioning

confidence: 99%

“…A mux-based thermometer code for the encoder Gray code is suggested in [2]. This has high speed and small region compared to wallace and Fat tree based encoders.…”

Section: Mux Based Encodermentioning

confidence: 99%

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019

ijrte

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“…The thermometer code is the output of the comparators and is converted to binary code by a binary encoder. Several encoders [7][8][9][10][11][12][13] are described in the literature, in which Fat-Tree encoder [14] exhibits better results as compared to others. For the design of encoders, complementary logic (CML) [15] based gates are efficient in terms of noise but power consumption is more due to extra biasing circuits.…”

Section: Introductionmentioning

confidence: 99%

“…For the design of encoders, complementary logic (CML) [15] based gates are efficient in terms of noise but power consumption is more due to extra biasing circuits. Pseudo-NMOS based encoder [10] is fast but has a large PMOS load which increases with the increase in number of inputs. MUX based encoder [12,13] is power efficient but slow as compared to Fat-Tree encoder [1,2,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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Design Procedure and Selection of TIQ Comparators for Flash ADCs

Abumurad

Choi

2017

Circuits Syst Signal Process

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A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique

Cited by 8 publications

References 13 publications

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Design Procedure and Selection of TIQ Comparators for Flash ADCs

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