A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications

Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node

“…In other words, the beta ratio of M3D SRAM cell can be adjusted without area penalty by changing the numbers of stacked MoS2 nanosheet FETs. The metal interconnect resistance increases significantly as technology node scales beyond 7nm node [1][2]. In order to release the impact of increased interconnect resistance, the metal line length of SRAM cell needs to be reduced.…”

“…The growing demand for AI applications is a major driver for reducing power and continued area scaling in SoCs (System-on-Chips). Continued scaling of the transistor and metal interconnection geometry is accompanied by the increased wire routing resistance which degrades the SRAM performance and array efficiency in advanced technology nodes [1][2]. The buried power SRAM [3] has been proposed to lower the bitline (BL) and wordline (WL) resistance and thereby enhances the write margin and performance even though the total capacitance per cell has been increased.…”

A Preliminary Study: Towards Parallel Garbage Collection for NAND Flash-Based SSDs

“…One block consists of 768 pages of which size is 16 KB. The density of SRAM is about 4.75M B/mm 2 [45]. Thus, the size of a data register would be 3.4 × 10 −3 mm 2 .…”

Xor-Cim

“…With the aggressive CMOS scaling, it is possible to hold most of the weights on-chip (e.g. 256 Mb SRAM demonstrated at 7nm by TSMC [16]). Enlarging on-chip SRAM capacity is helpful to minimize the energy consuming off-chip DRAM access.…”