A 8.8-ns 54×54-bit multiplier using new redundant binary architecture

Makino, Hiroshi; Nakase, Y.; Shinohara, Hirofumi

doi:10.1109/iccd.1993.393380

Cited by 22 publications

(23 citation statements)

References 7 publications

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“…In [5] a 64 ¢64 bit multiplier based on a redundant signed-digit binary adder tree was shown to yield a smaller critical path delay than the corresponding Wallace tree multiplier. A similar design for a fast 54 ¢54 bit multiplier was recently presented in [6].…”

Section: Introductionmentioning

confidence: 99%

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Phatak

Koren

1994

IEEE Trans. Comput.

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A novel hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike.We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the tradeoffs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times.In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.

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Section: Introductionmentioning

confidence: 99%

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Phatak

Koren

1994

IEEE Trans. Comput.

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“…Its performance is about 1.7 times that of the corresponding binary implementation [9] at normalized supply voltage and power dissipation.…”

Section: Introductionmentioning

confidence: 96%

Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application

1998

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“…An 8.8 ns 54;54-bit multiplier using redundant binary architecture Makino et al presented important work on redundant binary arithmetic in [13,22]. Makino's multiplier became the fastest multiplier of the time with an 8.8 ns multiply delay.…”

Section: 3mentioning

confidence: 99%