A 8-bit 500-KS/s low power SAR ADC for bio-medical applications

Chang, You-Kuang; Wang, Chao-Shiun; Wang, Chorng-Kuang

doi:10.1109/asscc.2007.4425772

Cited by 85 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…We can observe the mismatch error-shaping from element rotation. We also observe a relatively large dc offset component as predicted by Equation (10). Figure 6b shows the spectrum from simulations with the three-level switching.…”

Section: Mismatch Shaping With Split-array C-dacmentioning

confidence: 60%

“…The capacitive digital-to-analog converter (C-DAC) is a popular type of DAC, which produces output voltage through charge redistribution between capacitors. C-DACs are especially widely used as auxiliary DACs in analog-to-digital converters (ADCs) such as delta-sigma ADCs, SAR ADCs, or pipelined ADCs, which require DACs to produce feedback signal which should be compared with the input signal [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. An important characteristic of a C-DAC is the dynamic power consumption associated with the switching of the C-DAC.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

et al. 2023

View full text Add to dashboard Cite

Capacitive DACs (C-DACs) are widely used as stand-alone DACs or in an ADC as auxiliary DACs. An important performance metric of a C-DAC is its energy consumption and the linearity between the digital input and the analog output. In multi-bit C-DACs, the mismatch between the capacitors can degrade linearity, which can be important in high-resolution applications. In this work, we analyze the power consumption and linearity performance of a class of C-DACs called split-array C-DACs. We show that the simple element rotation technique, which is widely used to suppress the mismatch error of DACs, cannot be used with the power-efficient three-level switching scheme to effectively suppress the mismatch error. Then, we propose a switching scheme which can be used with the power efficient three-level switching and can suppress the in-band mismatch error effectively.

show abstract

Section: Mismatch Shaping With Split-array C-dacmentioning

confidence: 60%

Section: Introductionmentioning

confidence: 99%

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

et al. 2023

View full text Add to dashboard Cite

show abstract

“…Conventional capacitive switching timing with a 12-bit differential SAR ADC requires 12 2 and also uses lower pole plate sampling with high power consumption. Later, the energy-saving capacitive switching timing [4] was proposed by Taiwan University to reduce the energy of the conventional switching timing. The monotonic switching timing and capacitive switching timing based − CM V [5] were proposed to further reduce the power consumption of the switching timing.…”

Section: Timing Design For the Highest Position Split Switchmentioning

confidence: 99%

A SAR ADC with a higher precision bootstrap switch and highest split capacitor array

Guo

et al. 2023

Third International Conference on Digital Signal and Computer Communications (DSCC 2023)

View full text Add to dashboard Cite

The design of this paper is a 12bit SAR ADC,in order to optimize its performance and be able to achieve high accuracy, there are certain requirements for certain modules of the ADC. The design uses the bottom plate sampling, access to the common mode level Vcm on the upper pole plate of the DAC capacitor array is accessed by a higher precision bootstrap switch to reduce the non-linearity brought by the Vcm level access switch. By performing FFT simulation on the sampling points, it can be used at a sampling rate of 50Ms/s when the input signal frequency is 0.8301MHz and ENOB is 15.64bit. The capacitor array uses a combination of segmentation and splitting to greatly reduce the number of total capacitors, achieving only 188 unit capacitors, a 97.7% reduction in number compared to the conventional structure, for the entire ADC digital circuit The power consumption as well as the area of the ADC digital circuit has been significantly improved. The comparator uses a dynamic latching comparator to reduce power consumption while reducing the equivalent input noise of the comparator. The logic circuit uses dynamic SAR logic to control the analog-to-digital converter's successive comparisons. Sampling and analysis of the entire SAR ADC output achieves a valid bit count of 11.93 bits at a low frequency input signal of 0.1953MHz, enabling the conversion of a 12bit SAR ADC.

show abstract

“…O trabalho [28] propõe o chaveamento chamado de energy-saving. Dessa maneira, o consumo de energia médio, devido ao chaveamento no DAC, é diminuído em um percentual de 57% (usando o resultado da equação 2.16, nesse caso, ξ=0.…”

Section: Sinais De Controleunclassified

“…28) onde: K c é o parâmetro de densidade do capacitor, A é a área do capacitor, σ (∆C n /C n ) é o desvio padrão da variação relativa do C n e K σ é uma constante que descreve a variação aleatória do valor de C n . Desse modo, espera-se que quando a área do capacitor aumente, sua variação relativa ∆C n /C n diminuirá.…”

unclassified

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Gonzalez¹

View full text Add to dashboard Cite

This work presents the design of an 11 bits, 20-MS/s, Analog-to-Digital Converter (ADC) for an ultra-wideband (UWB) receiver applied in breast cancer detection in 180 nm CMOS technology.The architecture taken from the literature is known as successive approximation register (SAR). This architecture was selected because it is more efficient in energy terms compared to other architectures in order to achieve the design target of this project: a 20-MS/s ADC with a SNDR higher than 62 dB. A differential architecture was chosen to achieve a better common-mode disturbance rejection. The prototype ADC comprises a sample and hold circuit, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and the logic control circuit which implements the SAR algorithm. Merged capacitor switching procedure was implemented, therefore, the differential DAC capacitor network serves both to a top-plate sampling of the input signal and subtracts the reference in the conversion process. Furthermore, the 11 bit ADC takes advantage of using 10 bit DACs, saving power and area. An asynchronous operation was selected to eliminate the need for an external high-frequency clock. To improve the linearity, a delay cell inside the asynchronous clock generator is implemented, allowing a larger settling time for the capacitive DAC.The designed ADC occupies 0.1 mm 2 and post-layout simulation results show that it achieves an ENOB of 10.73 bit at a sampling rate of 20 MS/s and an input tone at Nyquist rate. The power consumption is 2.89 mW at 1.8 V supply, thus achieving the figure of merits of Schreier (FoM S ) and Walden (FoM W ), 162 dB and 84 fJ/conv.-step, respectively. At 20-MS/s, 1,8-V, the DNL is +0,32/-0,29 LSB and the INL is equal to +0,33/-0,26 LSB.Experimental measurements were carried out to determine the performance of the designed ADC. From these tests, non-linearity issues were detected on the output signal of the ADC. These problems in the experimental phase of the design were analyzed, and a hypothesis was proposed to explain them. Based on theoretical and simulation analysis, it was found which the non-linearity issues may have happened owing to the parasitic inductive effect of the wire bonded chip.

show abstract

A 8-bit 500-KS/s low power SAR ADC for bio-medical applications

Cited by 85 publications

References 3 publications

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

A SAR ADC with a higher precision bootstrap switch and highest split capacitor array

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Contact Info

Product

Resources

About