A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture

“…A dual-path charge-pump PLL type CDR employs a threestate phase and frequency detector in [6]. The phase detector is a half-rate multiplexed design.…”

Section: A Tri-state Phase Detectorsmentioning

confidence: 99%

Digital lock-detection for systematic phase noise elimination in a phase interpolator CDR

Ardalan

Feng

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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“…In this way, a dedicated lock detector is also not needed, and the transition between the frequency acquisition and the phase adjustment is robust and smooth. A similar technique, which was used in [21], also makes use of a weaker secondary loop that has negligible effect on the dominating loop while it is active.…”

Section: B Frequency Acquisition Mode and Phase Adjustment Modementioning

confidence: 99%

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

Huang

Cao

Green

2015

IEEE J. Solid-State Circuits

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An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 m CMOS is presented. By realizing an asymmetric phase detector transfer curve, the linear CDR's "single-sided" capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the need for the reference clock and the separate frequency detector in conventional dual-loop CDRs. Robust frequency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitter tolerance performance. The measurement results show that with a 10.3 Gb/s 2 -1 PRBS input, the random jitter at the output data is 0.336 ps , and the out-ofband jitter tolerance is 0.34 UI -.Index Terms-Analog, clock-and-data recovery (CDR), CMOS, jitter tolerance, linear phase detector, receiver, referenceless, wideband data communication. 0018-9200

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“…7 shows the block diagram of the binary half-rate CDR with the proposed UIA block, where we pass the data through a unit interval adjuster (UIA) block before it gets to the phase detector. Since the magnitude of the phase error is kept small, a binary PD [16] was used in the design. Fig.…”

Section: Proposed Half-rate Frequency Detectormentioning

confidence: 99%

“…Fig. 17 shows the implementation of a binary half-rate phase detector [16]. Here, and sample the data on the center and edge of the UI, respectively.…”

Section: Circuit Implementationmentioning

confidence: 99%

A Reference-Less Single-Loop Half-Rate Binary CDR

Jalali

Sheikholeslami

Kibune

et al. 2015

IEEE J. Solid-State Circuits

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This paper proposes a half-rate single-loop referenceless binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6 when it is activated. He has been engaged in research and design of high-speed IO with CMOS.

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A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture

Cited by 22 publications

References 5 publications

Digital lock-detection for systematic phase noise elimination in a phase interpolator CDR

Digital lock-detection for systematic phase noise elimination in a phase interpolator CDR

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

A Reference-Less Single-Loop Half-Rate Binary CDR

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