A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching

Huang, Hsi‐Ya; Lin, Jinyi; Hsieh, Chih-Cheng; Chang, Wen-Hsu; Tsai, Hann-Huei; Chiu, Chin‐Fong

doi:10.1109/iscas.2012.6271768

Cited by 11 publications

(12 citation statements)

References 9 publications

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“…7. The propagation delay is expressed in (3). The noise of the E/L detection circuit results in a jitter on the predefined delay and affects the accuracy of input-range detection as well.…”

Section: Proposed Sar Adc Architecturementioning

confidence: 99%

“…Thus, reducing DAC switching power is recently a crucial topic to improve the overall power efficiency. Several low-power DAC switching techniques have been published including energy saving [1], charge recycling switching (CRS) [2], input range prediction (IRP) [3], charge average switching (CAS) [4], charge recycling with LSB-down [5], set-and-down [6], merge-and-split (MS) [7], bidirectional single-side (BSS) [8], Manuscript V cm -based [9], and one-side switching instead (OSSI)+higherbit switching instead (HBSI) [10] to reduce the switching energy by 69%, 71%, 74%, 75%, 77%, 81%, 83%, 86%, 88%, and 97%, respectively, compared with the conventional approach [6]. The switching power can also be reduced by detecting the input range and skipping unnecessary switching.…”

Section: Introductionmentioning

confidence: 99%

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A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Lee

Lin

Hsieh

2016

IEEE Trans. Circuits Syst. I

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This paper presents a low-voltage and powerefficient 10 bit successive-approximation register (SAR) analogto-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a timedomain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm 2 . At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signalto-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3 µW to 2.5 µW and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.Index Terms-Low power, low voltage, SAR ADC.

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“…7. The propagation delay is expressed in (3). The noise of the E/L detection circuit results in a jitter on the predefined delay and affects the accuracy of input-range detection as well.…”

Section: Proposed Sar Adc Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Lee

Lin

Hsieh

2016

IEEE Trans. Circuits Syst. I

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“…On the contrary, moderate resolution ADCs having a sampling rate up to 1 MS/s are used in system-on-chip (SoC) measurement and wireless sensor networks [10][11][12]. Further the literature survey reveals efforts in the direction to use medium speed ADCs (few hundreds of kS/s) with circuit techniques for reducing power consumption in low bandwidth regime [13][14][15][16][17][18][19][20]. From another perspective, these designs intend to increase the ADC utilisation span over a broader frequency range without dissipating power in unnecessary switching.…”

Section: Introductionmentioning

confidence: 99%

Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components

Joshi

Shrimali

Sharma

2020

IET Circuits, Devices & Systems

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This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade-off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal-to-noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink ®. Furthermore, a fully differential 10bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves lowfrequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure-of-merit of 29.3 fJ/conv-step.

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“…As aforementioned, all of the previous work focuses on the target of lowering the power consumption of the DAC capacitor array and achieves improvement of energy efficiency in every conversion. Compared to the conventional switching scheme, the monotonic [25] and input range prediction [26] have reduced switching energy by 81% and 90% respectively.…”

Section: Bypass Window Techniquesmentioning

confidence: 99%

“…Many biomedical signals fluctuate within a very small range for a large portion of its period, as shown in Fig 3-14 which takes neural signal as an example [16]. For the previously mentioned structures [24]- [26], the ADC will not take this signal characteristic into account and work as normal. If an ADC can determine the magnitude of the input signal before starting conversion and change its switching sequences accordingly, then it is possible to reduce its activity when the input signal is located in a specified range.…”

Section: Bypass Window Techniquesmentioning

confidence: 99%

Design of a variable rate low power SAR ADC with bypass window for biomedical application

Liu¹

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This thesis is an elaboration of the past two years dedicated research work in NTU. It is a tough task and many have assisted me from various aspect. I would first express my gratitude to my supervisor, Assoc. Professor Yvonne Y.H. Lam, for providing me the opportunity to work in her group and guiding me to complete the project. Her continuous and patient teaching and support gives me a lot confidence and help me find excellent solutions for the problems in the project. I would also like to thank my senior, Dr. Yuan Chao, who spent valuable time to discuss papers and ideas with me. His comments always inspire me and help me dig down further into the problems which I encounter. I also appreciate his suggestion and advice on circuit design and simulations. I would also like to thank my friends and all the lab colleagues in the VLSI lab for all the happy hours we spent in lab and out of the lab. With you, life becomes colorful during the past two years in Singapore. I also want to thank the staff in VLSI lab for their help in software. Without the constant support and love from my parents and my younger sister, I would have never made it to this point. As a token of love and respect I dedicate this thesis to them. Finally, I acknowledge the financial support from Silicon Labs.

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A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching

Cited by 11 publications

References 9 publications

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components

Design of a variable rate low power SAR ADC with bypass window for biomedical application

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