A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology

Huang, Ke; Jia, Chen; Zheng, Xuqiang; Xu, Ni; Zhang, Chun; Rhee, Woogeun; Wang, Zhihua

doi:10.1109/iscas.2012.6271984

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“…That is because the system with source-synchronous structure is not only power efficient, but also has a good jitter performance [1]. A sourcesynchronous transmitter which is composed of five data lanes and one forwarded clock lane is designed in this paper.…”

Section: Introductionmentioning

confidence: 99%

A 10Gb/s source-synchronous transmitter in 65nm CMOS technology

Yuan

Zheng

et al. 2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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This paper describes the design of a sourcesynchronous transmitter in 65nm CMOS technology. The transmitter consists of five data lanes plus one forwarded clock lane. Every single lane works at 10Gb/s. The clock distribution path is carefully designed to ensure the synchronous of the divided clock in every data lane. And this design is power efficient by optimizing the structure of MUX. Furthermore, a 3 tap feed forward equalizer (FFE) is applied to the driver to compensate channel loss. The experiment result shows that, the output peak-to-peak jitter is 50ps when the transmitter delivers 10Gb/s PRBS7 data over a channel which has a loss of 12.3dB at 5GHz. The power consumption of this circuit is 6.1mW/Gbps for 1.2V supply and the chip area is 1.2mm 2 .. Keywords-transmitter; MUX; FFE; clock distributionI.

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Section: Introductionmentioning

confidence: 99%