A 9-Bit 10-MHz 28-$\mu$ W SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC

Janke, Devon; Monk, A.; Swindlehurst, Eric; Layton, Kent; Chiang, Shiuh–hua Wood

doi:10.1109/tcsii.2018.2845883

Cited by 12 publications

(6 citation statements)

References 11 publications

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“…However, for higher R re f cases, the required settling time exponentially decreases going down to the LSB conversion. Recent studies proposed a two-step delay technique [17] and an all-tapered delay technique [18] but neither proposed the impedance of R re f . According to Equations ( 2)-(4), increasing the resistance value leads to an increase in settling time.…”

Section: Equation Of Required Cdac Settling Time With Reference Buffermentioning

confidence: 99%

“…A two-step delay technique in high-resolution ADC [17] is proposed instead of utilizing different optimized delays in all conversion cycles for less hardware overhead. In addition, an all-tapered delay technique in mid-resolution ADC is proposed in [18] to reduce the conversion time even further. The previous works [17,18] studied the effect of the DAC switch but did not consider the impedance of the reference that is also a significant factor in determining the DAC settling time [19].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, an all-tapered delay technique in mid-resolution ADC is proposed in [18] to reduce the conversion time even further. The previous works [17,18] studied the effect of the DAC switch but did not consider the impedance of the reference that is also a significant factor in determining the DAC settling time [19]. In this paper, we analyze the effect of both reference and switch impedances and find that a tapering conversion of more than three becomes inefficient considering the hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

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A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

Kang

Lee

2023

Electronics

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A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply.

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Section: Equation Of Required Cdac Settling Time With Reference Buffermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

Kang

Lee

2023

Electronics

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“…Therefore, this paper focuses on digitally controlled delay generation methods with linear delay characteristics when the asynchronous SAR ADC has a sampling frequency of several MS/s. The linear delay characteristics can be applied to design the loop delay circuit of SAR ADC with reconfigurable sampling frequency or tapered bit periods [6,7]. For the SAR ADC of this paper, we designed an ADC with reconfigurable sampling frequency to obtain an adjustable frame rate in a touch screen panel (TSP) readout IC.…”

Section: Introductionmentioning

confidence: 99%

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

Lee

2019

Electronics

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An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 nm CMOS. The ADC occupies 0.054 mm2 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.

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“…Typical asynchronous architectures require a high-frequency input clock to generate a predetermined T/H period [9,10], and each clock cycle also needs a margin to account for clock jitter [11]. To alleviate speed limitations, alternative techniques like tapered clock generation are available [12]. For instance, to achieve a 25% T/H duty cycle, the input clock needs to be four times faster than the sampling clock frequency (fs).…”

mentioning

confidence: 99%

Asynchronous SAR ADC with self‐timed track‐and‐hold

Bae,

Lee,

Seong

et al. 2023

Electronics Letters

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This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases.

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A 9-Bit 10-MHz 28-$\mu$ W SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC

Cited by 12 publications

References 11 publications

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

Asynchronous SAR ADC with self‐timed track‐and‐hold

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