A 90 ns 100 K erase/program cycle megabit flash memory

Kynett, V.; Anderson, J.; Atwood, G.; Dix, P.; Fandrich, M.L.; Jungroth, O.; Kao, Soolin; Kreifels, J.A.; Lai, Sheng-Chih; Liou, H.-C.; Liu, B.; Lodenquai, R.; Lu, Wei-Ping; Pavloff, R.; Tang, Dongyan; Tsau, G.; Tzeng, Ju-Yuan; Vajdic, B.; Verma, G.; Wang, S.; Wells, S.; Winston, M.D.; Yang, L.

doi:10.1109/isscc.1989.48233

Cited by 4 publications

(3 citation statements)

References 3 publications

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“…Both types of redundancy circuits present difficulties, however. In a word line redundancy circuit, we must maintain consistency between the address order and the priority order, and in a bit line redundancy circuit, we must prevent failure due to "over-erasure" in unused bit lines [10].…”

Section: Word Line/bit Line Redundancy Circuitsmentioning

confidence: 99%

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

Miwa

Yamada

Hirota

et al. 1996

IEEE J. Solid-State Circuits

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This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 m 2 and a die size of 42.9 mm 2 have been achieved with 0.8 m design rules. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access.

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Section: Word Line/bit Line Redundancy Circuitsmentioning

confidence: 99%

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

Miwa

Yamada

Hirota

et al. 1996

IEEE J. Solid-State Circuits

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“…The cross sections of the FACE cell using 1 .O pm design rules are shown in Figure 2. The cell area of 8.4 pm2 represents 55% that of the conventional ETOX cell [4]. Using the IEDM 90-91 same process flow but 0.8 pm lithography rules, a 4.48 pm2 FACE cell is also fabricated.…”

Section: 11mentioning

confidence: 99%

“…The FACE memory technology utilizes the buried bitline approach [3] where the half contact per bit requirement of the conventional ETOX Flash memory is essentially eliminated [4]. Instead, the FACE array has one contact for every 16 rows (Fig.1).…”

Section: Introductionmentioning

confidence: 99%

A novel memory cell using flash array contactless EPROM (FACE) technology

Woo

Ong

Fazio

et al.

International Technical Digest on Electron Devices

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A new single transistor Flash memory cell which utilizes channel hot electron injection for programming and Fowler-Nordheim tunneling for erase is described. This Flash memory technology employs a "buried" N+ bitline to connect the memory transistors rather than metal and contacts. Elimination of contacts results in a 45% cell area shrink of the conventional ETOX" cell (based on 1.0 pm design rules). A 4.48 pm2 cell area is also realized by using a 0.8 pm technology. In addition to this tremendous cell scalability, the diffusion comer induced erase threshold "bimodality" can be reduced due to the intrinsic stripe geometries in the memory array. Furthermore, the ContacVMetal related layout rules can be relaxed which allows this contactless approach to be extended to future generations without requiring complicated contact processing. Hence, the Flash Array Contactless EPROM (FACE) technology lends itself to a very compact cell as well as a more manufacturable process.

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A 3D sidewall flash EPROM cell and memory array

Pein

Plummer

1993

IEEE Trans. Electron Devices

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A 90 ns 100 K erase/program cycle megabit flash memory

Cited by 4 publications

References 3 publications

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

A novel memory cell using flash array contactless EPROM (FACE) technology

A 3D sidewall flash EPROM cell and memory array

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