A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step

Transconductance improvement method for low-voltage bulk-driven input stage

“…With the development of portable and biomedical applications, low-voltage and low-power analog and mixed signal ICs are required in increasing demands [1][2][3]. One of the main analog building blocks is the operational transconductance amplifier (OTA), which is the largest and most power consuming [4,5].…”

A highly linear 1.2 V 12bit 5–45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing

“…However, ADCs with scalable speed and power are not as power efficient as ones with fixed sample rate, e.g., 10-bit programmable ADCs only show a FOM of 0.5 pJ/ conversion [4]. Opamp-sharing technique is an effective way to improve the power efficiency of pipelined ADCs, however, it has two serious problems, memory effects induced by the non-reset summing node and potential crosstalk between two successive stages caused by the parasitic capacitors of switches that are used to implement opamp-sharing.…”

High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier

“…For analog circuitry, however, the power consumption remains approximately constant regardless of the sampling frequency because static bias currents are used to keep transistors in the active region during the whole period of circuit operation. Previous publications on high-speed powerscalable ADCs achieved power-scalable functionality by adjusting the static bias current with the proper scaling factors according to the sampling frequency [1,2]. Nevertheless, this technique is only feasible for a small range of sampling frequencies because wide-range bandwidth adjustment requires a large variation in the bias current, which will push the MOS transistors of the current sources into a weak inversion regime when their bias currents are small.…”