2008
DOI: 10.1109/isscc.2008.4523258
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A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension

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Cited by 13 publications
(5 citation statements)
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“…The use of fine-scale, low voltage, high-g m digital processes is necessary as they are inherently faster than older and higher voltage processes. Additionally, wireline communication systems are moving towards single chip solutions [4], so a line driver implementation in the same digital CMOS process as the digital core is highly desirable.…”
Section: Introductionmentioning
confidence: 99%
“…The use of fine-scale, low voltage, high-g m digital processes is necessary as they are inherently faster than older and higher voltage processes. Additionally, wireline communication systems are moving towards single chip solutions [4], so a line driver implementation in the same digital CMOS process as the digital core is highly desirable.…”
Section: Introductionmentioning
confidence: 99%
“…Finally, a comparison table with other similar circuits is provided in Analytical analysis is provided on the switchable capacitive attenuation topology 1) Minimum NF at highest-gain setting (2) Maximum IIP3 at lowest-gain setting (3) s 21 (4) Uses a dedicated non-configurable amplifier for the highest-gain setting adding parasitic switch capacitances showing that the capacitor values can be selected in order to provide constant attenuation steps. This chapter also provides analytical The design section starts with the core concept of the DI topology and then continues with the full circuit schematic of the topology.…”
Section: Resultsmentioning
confidence: 99%
“…Overall, the presented double-input RFPGA topology provides a performance improvement in terms of chip area and bandwidth, while providing comparable performance in terms of noise figure, linearity and power consumption. ( 1) Minimum NF at highest-gain setting (2) Maximum IIP3 at lowest-gain setting (3) s 21 (4) Uses a dedicated non-configurable amplifier for the highest-gain setting Front-End Prototype The chapter is divided in five sections: mixer topology, front-end architecture, circuit design, experimental results and summary.…”
Section: Resultsmentioning
confidence: 99%
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