A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

Kumaki, Satoshi; Takata, Hitoshi; Ajioka, Yoshiaki; Ooishi, T.; Ishihara, Kengo; Hanami, A.; Tsuji, T.; Kanehira, Y.; Watanabe, Takahiro; Morishima, Chikayoshi; Yoshizawa, T.; Sato, H.; Hattori, Shinichi; Koshio, A.; Tsukamoto, K.; Matsumura, Toshiro

doi:10.1109/cicc.2001.929815

Cited by 12 publications

(2 citation statements)

References 8 publications

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“…This organization is very common and provides a suitable balance between cost and performance. As semiconductor technology progresses, single-chip MPEG-2 MP@ML encoders have integrated audio and system [8]- [11] while keeping the above-mentioned architectural characteristics. However, the optimum architecture for video encoding/decoding is different from that for audio and system encoding/decoding.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding simultaneously, but also MPEG-2 MP@HL decoding. Several MPEG-2 MP@ML video codecs [4], [7], MPEG-2 MP@ML video/audio/system encoders [8]- [11], and MPEG-2 MP@HL decoders [12]- [15] have already been reported. However, none of these previous circuits are capable of performing all these functions with a single integrated circuit.…”

Section: Introductionmentioning

confidence: 99%

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A single-chip MPEG-2 codec based on customizable media embedded processor

Ishiwata

Yamakage

Tsuboi

et al. 2003

IEEE J. Solid-State Circuits

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A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm 2 die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A single-chip MPEG-2 codec based on customizable media embedded processor

Ishiwata

Yamakage

Tsuboi

et al. 2003

IEEE J. Solid-State Circuits

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A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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SUMMARY This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.

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An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm

Tooyama

Takamatsu

Kodake

et al.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13um CMOS technology and contains approximately 7 M-transistors on 4.50"x 3.35" area. The estimated power consumption is less than lOOmW at SlMHz@l.OV. It features a Gradient Descent Search (GDS) algorithm that drastically reduces the required computation power to 7GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3port data cache SRAM with a writs disturb-free cell m y arrangement. The core can be applicable to a portable HDTV codec system. IntroductionA portable HDTV system such as a MPEG camera becomes more popular if people sends and receives a video mail using the broadband network. To realize a high quality and low power MPEG codec in the system, a highly efficient ME processor is essential, because the conventional ME technique requires more than 90% performance of the codec. Figure1 shows the power consumption trend of a ME processor. The power consumption in the 0.13um processor developed with the conventional technology is more than 1200mW even for 1/4 sub-sampling technique. This is too large for portable products.Several MPEG codec LSIs have been reported [I-31. These LSIs perform MP@ML video encoding. These cannot perform ME for HDTV resolution video with a single chip confieuration. 0.25 0.18 0.13 0 10 007 0.05 0 035 Silicon Technology [um]Fig. 1 Power Consumption Trend of ME Processor Figure2 shows the plot image of the newly developed ME processor. The features are as follows: 0 The GDS algorithm [4] is introduced for motion estimation. The GDS algorithm realizes ME for HDTV resolution video only with 7GOPS computation power, though the conventional full search (FS) algorithm requires about 1000GOPS.A SIMD datapath architecture optimized for the GDS algorithm is designed. The SIMD datapath contains 32 processing elements (PE). It can calculate mean square error (MSE) in 8 cycles per 1 macro block (MB). Its performance is lOGOPS at SlMHz@l.OV. It operates at low frequency and low voltage, so that its power consumption is quite low.The 32Kb 3-port SRAM macro that has a writsdisturbfree cell arrangement with a symmtrical memory cell layout is newly introduced. The estimated power consumption of this SRAM macro is 1.32mW at 1.OV and 81MHz. 0 0The above design techniques result in the realization of an ultra low power motion estimator. The characteristics of the motion estimator are as follows: 0 It can perfom ME for HDTV resolution video in realtime, assuming 1920 x 1080 pixels resolution, 30fps of frame rate, and*128 x 364 of search range. The estimated power consumption is less than lOOmW at the condition of 1.OV apply voltage and 81MHz clock frequency. 0

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A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

Cited by 12 publications

References 8 publications

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 codec based on customizable media embedded processor

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm

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