A Backside-Illuminated Image Sensor With 200 000 Pixels Operating at 250 000 Frames per Second

Son

Yamada

et al. 2013

Sensors

The ISIS is an ultra-fast image sensor with in-pixel storage. The evolution of the ISIS in the past and in the near future is reviewed and forecasted. To cover the storage area with a light shield, the conventional frontside illuminated ISIS has a limited fill factor. To achieve higher sensitivity, a BSI ISIS was developed. To avoid direct intrusion of light and migration of signal electrons to the storage area on the frontside, a cross-sectional sensor structure with thick pnpn layers was developed, and named “Tetratified structure”. By folding and looping in-pixel storage CCDs, an image signal accumulation sensor, ISAS, is proposed. The ISAS has a new function, the in-pixel signal accumulation, in addition to the ultra-high-speed imaging. To achieve much higher frame rate, a multi-collection-gate (MCG) BSI image sensor architecture is proposed. The photoreceptive area forms a honeycomb-like shape. Performance of a hexagonal CCD-type MCG BSI sensor is examined by simulations. The highest frame rate is theoretically more than 1Gfps. For the near future, a stacked hybrid CCD/CMOS MCG image sensor seems most promising. The associated problems are discussed. A fine TSV process is the key technology to realize the structure.

Section: Introductionmentioning

confidence: 99%

Toward One Giga Frames per Second — Evolution of in Situ Storage Image Sensors

Son

Yamada

et al. 2013

Sensors

“…However, the ISIS cameras [ 2 – 5 ] provide much better image quality, higher spatial resolution and wider applicability with the simple and compact structure. ISIS cameras have been tested for applicability in bio- and nano-science and engineering.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the authors started development of new image sensors that satisfy the two requirements: ultra-high speed and ultra-high sensitivity. The sensor is a backside illuminated ISIS (BSI-ISIS) [ 5 ]. The very high frame rate is achieved by employment of the ISIS structure on the front side; the very high sensitivity achieved by a combined use of three existing technologies: backside illumination, cooling and CCM, i.e.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Toward 100 Mega-Frames per Second: Design of an Ultimate Ultra-High-Speed Image Sensor

Dao

Tanaka

et al. 2009

Sensors

Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of each pixel to the input gate to the in situ storage area on the front side. The theoretical maximum frame rate is estimated at 100 Mega-frames per second (Mfps) by transient simulation study. The sensor has a spatial resolution of 140,800 pixels with 126 linear storage elements installed in each pixel. The very high sensitivity is ensured by application of backside illumination technology and cooling. The ultra-high frame rate is achieved by the in situ storage image sensor (ISIS) structure on the front side. In this paper, we summarize technologies developed to achieve the theoretical maximum frame rate, including: (1) a special p-well design by triple injections to generate a smooth electric field backside towards the collection gate on the front side, resulting in much shorter electron transit time; (2) design technique to reduce RC delay by employing an extra metal layer exclusively to electrodes responsible for ultra-high speed image capturing; (3) a CCD specific complementary on-chip inductance minimization technique with a couple of stacked differential bus lines.

“…In 2006, the color version, ISIS-V4, was reported [2]. In 2009, we developed ISIS-V12, a backside-illuminated image sensor mounting the ISIS structure and the CCM, charge-carrier multiplication, on the front side [3]. The CCM is a CCD-specific efficient signal-amplification device.…”

mentioning

confidence: 99%

A 16 Mfps 165kpixel backside-illuminated CCD

2011 IEEE International Solid-State Circuits Conference

Nguyen

Dao

et al. 2011

Self Cite

In 2002, we reported a CCD image sensor with 260×312 pixels capable of capturing 103 consecutive images at 1,000,000 frames per second (1Mfps) [1]. We named the sensor "ISIS-V2", for In-situ Storage Image Sensor Version 2. 103 memory elements are attached to every pixel; generated image signals were instantly and continuously stored in the in-situ storage without being read out of the sensor. The ultimate high-speed recording was enabled by this parallel recording at all pixels. In 2006, the color version, ISIS-V4, was reported [2]. In 2009, we developed ISIS-V12, a backside-illuminated image sensor mounting the ISIS structure and the CCM, charge-carrier multiplication, on the front side [3]. The CCM is a CCD-specific efficient signal-amplification device. CCM, combined with the BSI structure and cooling, achieved very high sensitivity. The ISIS-V12 was a test sensor intended to prove the technical feasibility of the structure. The maximum frame rate was 250kfps for a charge-handling capacity of Q max =10,000e -and 1Mfps for a reduced Q max . The pixel count was 489×400 pixels. For backside-illuminated (BSI) image sensors, metal wires can be placed on the front surface to increase the frame rate without reducing fill factor or violating uniformity of the pixel configuration. It has been proved by simulations that 100Mfps is achievable by introducing innovative technologies including a special wiring method [4]. We now report on ISIS-V16, developed by incorporating technologies to increase the frame rate with those to achieve very high sensitivity, which was confirmed by evaluation of ISIS-V12. The performance specification of ISIS-V16 is summarized in Fig. 23.4.1. Figure 23.4.2 shows the global planar structure of ISIS-V16. The imaging area is divided into 4 rectangular subareas. A set of driving voltages used in the image-capturing operation, which requires very high frequency, is transferred from the left and right, toward the vertical center-line through metal inner bus lines. The very wide inner bus lines, significantly reduce the resistance. The inner bus lines are connected to the outer metal bus lines with a special shape, named "Thunderbolt bus lines," which also serve to reduce the resistance in transferring the driving voltages.Figs. 23.4.3 and 23.4.4 depict the plane structure, installed on the front side, and a cross-section taken along the A-A' line in Fig. 23.4.3. In Fig. 23.4.4, incident photons generate electron-hole pairs in the thick p -generation layer. The generated electrons travel to the collection gate on the front side to form a signal charge packet. The charge packet is then transferred along an n + CCD channel, which is a memory device extending linearly in a slightly slanted direction to the orthogonal direction to the sheet, as shown in Fig. 23.4.3.In Fig. 23.4.3, a signal charge packet is transferred from the collection gate to the memory CCD channel, carried downward and drained from the drain at the end of the CCD channel. Therefore, a sequence of the latest image signals is always ...