A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Jeon, Hyung-Joon; Kulkarni, R. N.; Lo, Yung-Chung; Kim, Jusung; Silva-Martí­nez, J.

doi:10.1109/jssc.2013.2253414

Cited by 34 publications

(8 citation statements)

References 25 publications

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“…The adaptation of ADPLL filter coefficients efficiently minimized the jitter against PVT variations. Jeon et al [23] enhanced the Clock and Data Recovery (CDR) jitter performance with the inherent Bang-Bang Phase Detector (BBPD). The adaptive adjustment loop gain on the basis of estimated jitter spectrum provides the PVT insensitive and power loop gain.…”

Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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“…The FD gain is the same for both fine and coarse frequency loops. For both FLL and PLL, the digital loop filter is used to avoid the huge capacitors [21,22]. The circuit operations of the coarse FD, the fine FD, and the ICO are explained in the following paragraphs.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…The analog type uses parallel charge-pump circuits [22] that are turned on or off by a thermometer code. The digital type uses parallel switches at the VDD side of DCO [24] that are turned on or off by a thermometer code.…”

Section: Adaptive Bw Tracking Icomentioning

confidence: 99%

“…The digital type uses parallel switches at the VDD side of DCO [24] that are turned on or off by a thermometer code. Both [22] and [24] are the reference-based CDRs. The adaptive bandwidth scheme was not published for the referenceless CDRs.…”

Section: Adaptive Bw Tracking Icomentioning

confidence: 99%

“…8. Compared to the analog type CDR [22], the proposed adaptivebandwidth CDR has a smaller phase noise and a smaller area. Compared to the conventional digital type CDR [24], it has a better immunity to VDD noise, a smaller area, and a better linearity.…”

Section: Adaptive Bw Tracking Icomentioning

confidence: 99%

See 2 more Smart Citations

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

Kwon¹,

Lim²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

show abstract

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Cited by 34 publications

References 25 publications

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

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