A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Shan, Weiwei; Dai, Wentao; Wan, Liang; Lu, Minyi; Shi, Longxing; Seok, Mingoo; Yang, Jun

doi:10.1109/jssc.2019.2959494

Cited by 16 publications

(5 citation statements)

References 42 publications

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“…7 shows the overall architecture of the proposed DVS design based on CPR techniques. A transition detector is proposed along with the latch-based Error Detection and Correction (EDAC) method, which has also been widely used [29,30,31,32,33]. The blue box at the end of the replica path represents the transition detector (TD) cell, which will generate an ERR signal when the entire replica path's delay beyond the clock cycle, i.e.…”

Section: Dvs Architecture and Transition Detector Designmentioning

confidence: 99%

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Liu

Wang

Yin

et al. 2024

IEICE Electron. Express

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Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an 'error' signal used to dynamically regulate the chip's operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

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Section: Dvs Architecture and Transition Detector Designmentioning

confidence: 99%

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Liu

Wang

Yin

et al. 2024

IEICE Electron. Express

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“…Southeast University proposed a bidirectional adaptive clocking circuit to provide zero-delay fine frequency tuning for AVFS system [39,40] . It can compress the cycle when the timing margin is too much, or extend the clock cycle when the timing is wrong to ensure correct function.…”

Section: Adaptive Clocking Avfs Systemmentioning

confidence: 99%

Near-Threshold Wide-Voltage Design Review

Zhao

Yang

Chen

et al. 2023

Tsinghua Sci. Technol.

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This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3-4 times.

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“…Based on the 28nm process library, Monte Carlo simulations of the above cells with the basic drive strengths are performed to obtain delay variability. And the cells with other drives can be calculated according to (2).…”

Section: The Fo4 Inverter Chain Basic Cells and Basic Path For Verifi...mentioning

confidence: 99%

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

Cui

Shan

Dai³

et al. 2023

Chinese J. Elect.

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In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths' latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been proven to be a good metric to estimate the path's delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study, an improved model of path delay variability is established to describe the relationship between the paths' max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs (i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and 40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips' measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages. Key words -Modeling, Process, voltage, and temperature (PVT) variations, Delay variability, Digital integrated circuit and FO4 inverter chain.

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A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Cited by 16 publications

References 42 publications

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Near-Threshold Wide-Voltage Design Review

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

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