A BICS for CMOS opamps by monitoring the supply current peak

Font, J.; Ginard, J.; Isern, E.; Roca, M.; Segura, J.; Garcia, EA

doi:10.1109/olt.2002.1030190

Cited by 7 publications

(6 citation statements)

References 9 publications

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“…techniques [1][2][3], commonly referred to as IDDQ current sensors, are relatively simple as no test stimulus block A is required, and suitable for detecting bridging faults. However, a Circuit-Under-Test (CUT) may suffer from power supply variations caused by a shunt resistive component connected between the CUT and power supply (or ground), and inappropriate setting of reference currents may also affect the precision of fault detection owing to a broad range of faulty currents [4].…”

Section: Existing On-chip Testing Tech-niques and System Implementa-t...mentioning

confidence: 99%

“…Therefore, there is Manuscript received on July 14, 2009 ; revised on October 23, 2009. 1,2 The authors are with The Electronic and Photonic System Engineering, Kochi University of Technology (KUT), Tosayamada-Cho, Kami-City, Kochi, 782-8502, Japan. Tel: (+81)-887-57-2212, E-mail: 118002m@gs.kochi-tech.ac.jp and tachibana.masayoshi@kochi-tech.ac.jp a demand for cost-effective test techniques with low testing time.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

San-Um

Tachibana

2009

ECTI-EEC

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This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable delay line for generating pulse stimuli, and a sample-and-hold circuit with comparators for fault detection process. Demonstrations of the testing for a Sallen-Keylow-pass ¯lter using 0.18-?m CMOS technology yields relatively high fault coverage. The fault coverage of catastrophic faults is 100%, and the fault coverage of capacitor and resistor variations are 93.75% and 87.5%, respectively. The proposed BIST technique uses low testing time within two short pulse response waveforms, and o®ers low implementation cost since onchip sinusoidal stimuli, test algorithms, and external digital processing unit are not necessary.

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Section: Existing On-chip Testing Tech-niques and System Implementa-t...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

San-Um

Tachibana

2009

ECTI-EEC

View full text Add to dashboard Cite

show abstract

“…The observability of the supply current can be easily achieved by measuring the voltage drop. But this method has a shortcoming of impacting the effective supply voltage range seen by the device under test (DUT) and requires precise current sources [4,10]. A built-in self test (BIST) scheme effectively configures the op amp as a voltage follower and a comparator to detect its slew rate deviation and signal propagation delay deviation, respectively [19].…”

Section: Introductionmentioning

confidence: 99%

Digital-Compatible Testing Scheme for Operational Amplifier

Ting

2012

J Electron Test

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This paper presents a digital-compatible testing scheme for operational amplifier (op amp). In the proposed scheme, the op amp device under test (DUT) is configured to a unity-gain buffer which is responded to a testing pulse, could be realized by a ring oscillator circuit. The output of the configured unity-gain buffer is digitized by simple digital counter and then the digitized counting number is compared to a predetermined critical value to evaluate the op amp DUT. The digitized counting number is sensitive to the specification of op amp DUT and easily to be observed in the digital domain. The testing parameters of testing setup of stimulus, testing result, testing accuracy, and testing time are also investigated to detail the proposed scheme. Digital compatibility and simplicity are main advantages of the proposed testing scheme. In addition, no complicated analog comparator and reference voltages are required. Behavioral and circuit level simulations are performed to show the effectiveness of the proposed scheme.

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“…Two major testing techniques are current and voltage sensing techniques. On the one hand, the current sensing technique, commonly referred to as IDDQ and IDDT current sensors [2][3], is relatively simple and suitable for detecting bridging faults. However, a Circuit-Under-Test (CUT) may suffer from power supply variation, and inappropriate setting of reference currents may affect the precision of fault detection.…”

Section: Introductionmentioning

confidence: 99%

An On-Chip Analog Mixed-Signal Testing Compliant with IEEE 1149.4 Standard Using Fault Signature Characterization Technique

San-Um

Tachibana

2009

ECTI-EEC

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An on-chip analog mixed-signal testing, compliant with IEEE 1149.4 standard is presented. The testing technique is based on sinusoidal output response characterizations, yielding a complete detection of AC and DC fault signatures without a need for simulation-before-test process. The testing system is an extension of IEEE 1149.4 standard, and affords functionalities for both pre-screening on-chip and high-quality o®-chip testing. A 4th-order low pass Gm-C ¯lter was employed as a circuit-under-test, and implemented with the proposed testing approach in a physical level using 0.18-m CMOS technology, and simulated using Hspice. The maximum operating frequency of the testing circuit is 260MHz. Both catastrophic and parametric faults are potentially detectable with low performance degradation. The fault coverage of faults associated in CMOS and capacitors are relatively high at 94% and 100%, respectively.

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A BICS for CMOS opamps by monitoring the supply current peak

Cited by 7 publications

References 9 publications

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

Digital-Compatible Testing Scheme for Operational Amplifier

An On-Chip Analog Mixed-Signal Testing Compliant with IEEE 1149.4 Standard Using Fault Signature Characterization Technique

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