A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning

Abstract

This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ADC. The proposed ADC integrates a stochastic flash ADC (SF-ADC) into a successive approximation register ADC (SAR-ADC) to enhance its resolution. The SF-ADC is also used as a digitally controlled variable threshold comparator to provide error correction of the SAR-ADC. The proposed system also calibrates the ADC error using the machine learning algorithm on an external PC without additional power dissipation at a sensor node. Due to the flexibility of the system, the design complexity of an AFE IC can be relaxed by using these techniques. The target resolution is 18 bits, and the target bandwidth (without digital low-pass filter) is about 5 kHz to deal with several types of biopotential signals. The design is fabricated in a 130-nm CMOS process and operates at 1.2-V supply. The fabricated ADC achieves the SNDR of 88 dB at a sampling frequency of 250 kHz by using the proposed calibration techniques. Due to the high-resolution ADC, the input-referred noise is 2.52 µV rms with a gain of 28.5 dB.

Evaluation of In Vivo Spike Detection Algorithms for Implantable MTA Brain—Silicon Interfaces

“…This reduces the FoM of each algorithm, increasing the resources required by each operation without bringing any advantages. It is possible to define a typical samples bit range laying under 8-10 bits, but the literature present different methods that allow one to improve the analog to digital converter (ADC) performances in power-constrained applications [17], lowering the required bit number without losing precision.…”

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

“…As provided previously in Table 1, recent SAR ADC architectures add specific compression as in [27,29] or are combined with a further data compression block. Both must reduce the large amount of data delivered by the SAR ADC as in [25] to reduce the data amount to be sent to the control unit.…”

“…Another SAR ADC-based proposal is to sample the ECG signal at two different sampling frequencies which are selected according to its analog slope extraction [26]. Additionally, authors in [27] propose a high-precision ECG sensor system due to an ADC that integrates a stochastic flash ADC with a digitally controlled variable threshold comparator into a SAR ADC. In addition, a dynamic tracking SAR ADC and a hybrid SAR-sigma-delta ADC are proposed in [28,29], respectively.…”

“…Therefore, some of the most recent SAR ADCs are summarized in Table 1 in reference to different resolutions, m, that are sorted from low to high values. In fact, there are proposals to reduce the data length of the SAR ADC output [14,[24][25][26]28] and others to increase SAR ADC resolutions [27,29]. For the data length reduction, the SAR ADC in [28] uniformly samples the ECG signals, and then, a digital signal processing is operated.…”

“…They are the frequency of the successive approximation of registers (SARs), F SAR , the sample-and-hold frequency or the reference frequency, F ref , the dynamic range, the complementary metal oxide semiconductor (CMOS) technology, the power consumption and the core area, and the effective number of bits (ENOB) is presented in Table 1. The ENOB is given in the reference or is extracted from the signal-to-noise and distortion ratio (SNDR) in decibels (dB) as in (1) [27].…”