A bipartite, differential I/sub DDQ/ testable static RAM design

Abstract

IDDQ or current testing has emerged in the last f e w years as a n effective technique for detecting certain classes of faults in high density IC's. In this paper a testable design that enhances the IDDQ testability of static random access m e m o r i e s (SRAMs) f o r oflline testing is proposed. To achieve high accuracy and a test speed approaching t h e s y s t e m operational speed, the m e m o r y is partitioned f o r comparison of IDDQ values. Parallel write/read operations are used t o activate possible faults, whale quiescent power supply currents f r o m t w o blocks are compared.