Proceedings of the IEEE 2013 Custom Integrated Circuits Conference 2013
DOI: 10.1109/cicc.2013.6658533
|View full text |Cite
|
Sign up to set email alerts
|

A bipolar >40-V driver in 45-nm SOI CMOS technology

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2014
2014
2024
2024

Publication Types

Select...
4
1

Relationship

1
4

Authors

Journals

citations
Cited by 6 publications
(1 citation statement)
references
References 9 publications
0
1
0
Order By: Relevance
“…For higher power delivery over the optimal BCP frequency span (up to 80 MHz [7]), an HV driving stage is designed at the BS TX. Compared with the implementations in the HV or SOI process [28], standard CMOS-compliant designs use the stacked MOS configurations with corresponding biasing techniques to tackle the overstress and gate-oxide reliability issue [22], [29], [30]. Serneels et al [29] and Luo and Ker [30] introduced the self-generated and adaptive gate biasing techniques, respectively.…”
Section: Charge-replenishing High-voltage Drivermentioning
confidence: 99%
“…For higher power delivery over the optimal BCP frequency span (up to 80 MHz [7]), an HV driving stage is designed at the BS TX. Compared with the implementations in the HV or SOI process [28], standard CMOS-compliant designs use the stacked MOS configurations with corresponding biasing techniques to tackle the overstress and gate-oxide reliability issue [22], [29], [30]. Serneels et al [29] and Luo and Ker [30] introduced the self-generated and adaptive gate biasing techniques, respectively.…”
Section: Charge-replenishing High-voltage Drivermentioning
confidence: 99%