A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology

Ismail, Yahya A.; Lee, Haechang; Pamarti, Sudhakar; Yang, Chih-Kong Ken

doi:10.1109/jssc.2016.2636876

Cited by 31 publications

(10 citation statements)

References 17 publications

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“…In [10] and [13], high voltage gains were achieved, but at the cost of using an extremely large area. In [14], a small area was used for a charge pump, but the voltage gain was much lower than the required voltage gain of this work. This paper presents our implementation of multiple charge pumps that exhibit very high voltage gain and low area.…”

Section: Introductionmentioning

confidence: 95%

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

Toft

Jørgensen

2021

ELEKTRON ELEKTROTECH

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This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

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Section: Introductionmentioning

confidence: 95%

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

Toft

Jørgensen

2021

ELEKTRON ELEKTROTECH

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“…The output voltage of the Dickson charge pump II is higher than the well/substrate breakdown voltage, so the conventional diodes should not be utilized in the second sub-stage to avoid destroying the circuit. Planting the diodes in a deep n-well is an approach to overcome the single p-n junction limit and supports a maximum output level up to twice the breakdown voltage [24,27]. This structure is shown in Figure 2.…”

Section: Design Of the Charge Pumpmentioning

confidence: 99%

A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

et al. 2019

Sensors

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Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18-μm standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm2. Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at −40∼80∘normalC are less than 1.1%.

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“…Standard nanometre-scale technology can be used to reach output voltages as high as 36 V [7] but this is possible only for small output currents. Another option is to use Bipolar-CMOS-DMOS (BCD) [8] technology which incorporates high-voltage capabilities but usually comes with higher manufacturing costs.…”

Section: Introductionmentioning

confidence: 99%

High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area

2021

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A hybrid charge pump was developed in a 0.13-µm Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of zero-reversion loss cross-coupled stages and a new, self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.INDEX TERMS Charge pump, high-voltage, hybrid, BCD, small-area, cross-coupled, serial-parallel.

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A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology

Cited by 31 publications

References 17 publications

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area

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