This paper deals with system-level optimization of a digital-to-analog converter (DAC) for hearing-aid audio Class D output stage. We discuss the ΣΔ modulator system-level design parameters-the order, the oversampling ratio (OSR) and the number of bits in the quantizer. We show that combining a reduction of the OSR with an increase of the order results in considerable power savings while the audio quality is kept. For further savings in the ΣΔ modulator, overdesign and subsequent coarse coefficient quantization are used. A figure of merit (FOM) is introduced to confirm this optimization approach by comparing two ΣΔ modulator designs. The proposed optimization has impact on the whole hearing-aid audio back-end system including less hardware in the interpolation filter and half the switching rate in the digital-pulse-width-modulation (DPWM) block and Class D output stage.

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Abstract-In this paper a full high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in ultrasound medical applications is designed and implemented in a 0.35 µm high-voltage CMOS process.The CMUT is single-ended driven. The design is taped-out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area occupied by the design is 0.938 mm 2 and the maximum power consumption is 187.7 mW.

Increasing the switching frequency for switch mode power supplies is one of methods to achieve smaller, lighter weight and cheaper power converters. This work investigates the opportunity of using two layer circular spiral inductors implemented in a 150 µm finished thickness printed circuit board for a high frequency DC-DC converter. The inductor was tested in a 5 W buck converter switching at 10 MHz. The converter achieved 84.7% peak efficiency converting 12 V to 5 V and 78% efficiency converting 24 V to 5 V.

Abstract-This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch levelshifter has a superior power consumption of 1800 µW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 µW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 µW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03 ns/(0.35 µm 50 V) = 0.12 ns/µm V.