High-voltage pulse-triggered SR latch level-shifter design considerations

Abstract

Abstract-This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch levelshifter has a superior power consumption of 1800 µW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 µW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 µW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03 ns/(0.35 µm 50 V) = 0.12 ns/µm V.

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

“…This means that considering both FoM and implementation cost, the proposed HVLS outperforms [15,16]. It is worth mentioning that the structures, such as [4,14,16,24], having reasonably low FoM (in the order of magnitude of 10 -1 ) and without boost capacitor, adopt a technique called "Pulse-triggered". The "Pulse-triggered" technique can also significantly reduce the transfer delay and power dissipation.…”

“…It is widely used in multi-rail power supply on-chip systems, such as Very Large Scale Integration circuit (VLSI), Micro-Electro-Mechanical Systems (MEMS), mixed-signal integrated circuits and power-conversion systems [1][2][3][4][5][6][7][9][10][11][14][15][16][17][18][20][21][22][24][25][26].…”

“…For high voltage applications [4][5][6][7]11,[14][15][16][17]18,22,24], the recent years growing markets in smart electronic vehicles, renewable energy systems, high-brightness LED lighting systems, and MEMS MOSFETs have advantages of significantly lower on-resistance and threshold voltage than those of the thick-oxide devices [22]. However, the thin-oxide high-voltage MOSFETs have limitations on VGS (voltage difference from gate to source terminals of transistor) swing.…”

High-voltage integrated transmitting circuit with differential driving for CMUTs

“…Even though this topology is used in circuits with low-power requirements [5], it can present some problems such as large area due to the high gate-source voltage range, unregulated current pulse magnitude that controls the state of the latch and latch start-up state issues when ramping the high-voltage domain of the level shifter. In order to overcome some of these problems an improved version of the pulse-triggered level shifter presented in [10] is used and its schematic is shown in Fig. 8.…”

Integrated differential high-voltage transmitting circuit for CMUTs

“…The previous pulse-triggered level shifters that were used in [2], even though they were functional, presented some problems such as large area due to the high gate-source voltage range, unregulated current pulse magnitude that changes the state of the latch and latch start-up state issues when ramping the high-voltage domain of the level shifter. In order to overcome some of these problems a new improved version of the pulse-triggered level shifter presented in [4] is used in this transmitting circuit and its schematic is shown in Fig. 3.…”