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Abstract-In this paper a full high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in ultrasound medical applications is designed and implemented in a 0.35 µm high-voltage CMOS process.The CMUT is single-ended driven. The design is taped-out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area occupied by the design is 0.938 mm 2 and the maximum power consumption is 187.7 mW.

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Abstract-This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch levelshifter has a superior power consumption of 1800 µW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 µW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 µW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03 ns/(0.35 µm 50 V) = 0.12 ns/µm V.

Abstract-This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0-100 pF capacitive load. The design has been implemented in a 0.18 µm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V -1.4 V supply. A current step load from 250-500 µA with an edge time (rise and fall time) of 1 ns results at ∆Vout of 64 mV with a settling time of 3 µs when C L = 0. The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.