Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

Yosef-Hay, Yoni; Muntal, Pere Llimos; Larsen, Dennis Oland; Jørgensen, Ivan Harald Holger

doi:10.1109/norchip.2016.7792888

Cited by 7 publications

(7 citation statements)

References 9 publications

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“…This leads to a dominant pole configuration with little stability issues. The high mobility of electron carriers in nMOS devices allows lower device size for a specific current [ 10 ]. Despite these features, they suffer from a few problems among them the most important ones are as follows: The common drain configuration provides a voltage gain of lower than one for nMOS pass transistors.…”

Section: Ldo Linear Regulator Design Foundationsmentioning

confidence: 99%

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Bahramali

López‐Vallejo

2021

Micromachines

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There are emerging applications, like bridge structural health monitoring, continuous patient condition and outdoor aiding of the elderly and the disabled, where Internet of things (IoT) nodes are used with very limited accessibility and no connection to the main supply network. They may also be exposed to harsh environmental conditions. These are applications where power and available area constraints are of great concern. In this paper, we design a 1.1 V low dropout (LDO) linear regulator in 40 nm technology to be embedded in IoT nodes. To address these constraints, we used state-of-the-art, variability-aware resistor-less sub-threshold biased CMOS-only ultra low power consumption configurations having low active area. The proposed LDO is internally compensated with embedded 18 pF Miller and 10 pF load capacitances. It can supply 1 mA maximum load current with 0.8 uA quiescent current. The dropout voltage of the regulator is 200 mV with minimum input voltage of 1.3 V. The efficiency of the regulator is 84%, which is about 99% of the maximum achievable efficiency for a 200 mV dropout voltage. The whole circuit, consisting of the embedded voltage reference and the Miller and load capacitances, takes less than 0.007 mm2 of the die size with 1 W power consumption.

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Section: Ldo Linear Regulator Design Foundationsmentioning

confidence: 99%

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Bahramali

López‐Vallejo

2021

Micromachines

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“…A simple linear voltage regulator consists of a basic control loop where a negative feedback is compared to an internal reference in order to provide a constant voltage regardless of changes or perturbations in the input voltage, temperature, or load current [16][17][18][19]. Some of voltage regulator are performed in switching configuration [20].…”

Section: Ldo Topologymentioning

confidence: 99%

Design consideration in low dropout voltage regulator for batteryless power management unit

Kamel¹,

Wong²

2019

Bulletin EEI

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Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

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“…Where, ∆V OU T,pp is the sum of the undershoot and overshoot and K is the edge time ratio which is defined by K = ∆t used in the measurement smallest ∆t among the designs for comparison (10) The unit of the F oM is volt as noted in Table 2. The K factor depends on the designs considered for comparison, because the edge time of our simulation work is the smallest, it K factor is equal to 1 while for the measurements results the edge time of 1.5 µs will result in K = 1500.…”

Section: Performance Comparisonmentioning

confidence: 99%

“…This paper is an extended version of the work in [10] published in IEEE International Nordic Circuits and Systems Conference (NORCAS) in 2016.…”

Section: Introductionmentioning

confidence: 99%

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

Yosef-Hay

Larsen

Muntal

et al. 2017

Analog Integr Circ Sig Process

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This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0-100 pF capacitive load. The design has been taped out in a 0.18 µm CMOS process. The proposed regulator has a low component count, area of 0.012 mm 2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0 V -1.4 V supply. The measured results for a current step load from 250-500 µA with a rise and fall time of 1.5 µs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of 3.5 µs when C L between 0-100 pF. The proposed LDO regulator consumes a quiescent current of only 10.5 µA. The design is suitable for application with a current step edge time of 1 ns while maintaining ∆V out of 64 mV.

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Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids

Cited by 7 publications

References 9 publications

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Design consideration in low dropout voltage regulator for batteryless power management unit

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

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