A BIRA Algorithm for Embedded Memories with 2-D Redundancy

Abstract

One technique to increase the yield of memories is to incorporate spare rows columns into the main memory array. However, due to the long bit-line and line lengths in today's SOC technology, it is not efficient to replace faulty cells with a spare row or a spare column. Therefore, the redundant rows (columns) are divided into row (column) blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. We first propose a redundancy analysis algorithm suitable for built-in implementation or embedded memories with 2-D extended local repair-most algorithm, Due to the efficient utilization of redundant the manufacturing yield and reliability can be improved significantly. Thereafter, a simulator is implemented with language for evaluating the repair rates of the proposed algorithm. Simulation results show the proposed approach can increase the repair rate and fabrication yield significantly.