A BISR Architecture for Embedded Memories

Abstract

In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.

A bit level area aware cache-based architecture for memory repairs

“…Section IV concludes with the results for the benchmark 16Mbit (256Kx64) Memory Under Repair, demonstrating that the proposed memory BISR architecture is able to provide similar repairability results with the previous scheme of [18] on a reduced area overhead.…”

“…The difference between the scheme described in [18], onwards referred as non-segmented, and the present work's scheme, is that in case of a repair we choose to perform replacements at the bit level (d=1) instead of at the word level (d=M). Essentially, we downsize the data field from M bits to 1 bit and dedicate an m-bit offset pointer alongside the flag and tag fields, which identifies the specific bit that needs replacement.…”

“…In [18], it was shown that the area overheads of the nonsegmented memory BISR scheme on the benchmark MUR that has been studied were relatively small, even for high defect densities (less than 2% for 512 defective bits). We will now show that the segmented cache-bank scheme offers further area savings.…”

“…In [18], the authors proposed a cache-based memory BISR architecture for high defect densities that performs well at both key attributes and repairs defects occurring in the memory cell area by replacing complete faulty words with spare ones allocated in the spare cache-banks. Each cache-like bank uses a mechanism similar to that of direct-mapped cache memory in order to map faulty words to spare words.…”

“…Section III compares the area overheads of the scheme shown in [18] with the one presented in this work. Analytical calculations are made in order to show the gains of the proposed architecture.…”