A BIST Circuit for DLL Fault Detection

Jia, Chen; Milor, Linda

doi:10.1109/tvlsi.2008.2001732

Cited by 3 publications

(3 citation statements)

References 23 publications

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“…Thus, the DOT method is mainly discussed here. A BIST circuit for PLL fault detection is proposed in [15]. To instead break the loop by inserting a MUX, the author inserts a small loading capacitance at the inputs of the phase detector to measure phase offset.…”

Section: Previous Workmentioning

confidence: 99%

“…Many different structures of time‐to‐digital converter have been used in the method, such as that based on the delay line, the Vernier ring oscillator, and the time‐to‐voltage converter. Though it achieves a very excellent time resolution, the additional test circuits are usually too complex with high area overhead. Defect‐oriented test (DOT) [15–22]. …”

Section: Previous Workmentioning

confidence: 99%

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All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Xia

Tang

2020

IET Circuits, Devices & Syst

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Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Xia

Tang

2020

IET Circuits, Devices & Syst

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“…The DLL in the receiver is not tested completely by this BIST. This DLL can be treated as a stand-alone unit and using the techniques reported in [11], [12] a complete test of the DLL can be integrated with the interconnect test.…”

Section: Bistmentioning

confidence: 99%

Testable Design of Repeaterless Low Swing On-Chip Interconnect

Kumar

Sharma

2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.

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