All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Abstract

Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

“…Furthermore, a BIST scheme may be designed and appropriate for generic use or as a one-off solution. That is, the scheme may be applicable to any circuits class [12,13], specific to a given class [14,15], or even tailored to individual intra-class circuit architectures [16,17]. Generic defect-oriented paradigms employ topology transforming techniques by integrating oscillation-based mechanisms [10,18] or using structures such as pull-up/pulldown transistors [8].…”