A boundary scan test controller for hierarchical BIST

Abstract

A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

A processor for testing mixed-signal cores in System-on-Chip

“…These include self-testing [3], memory tests [10], and the entire test of a SoC [6]. Both hardware and software specific facilities can be provided in these processors, such as boundary-scan controllers [9], Linear Feedback Shift (LFSR) and Multiple Input Shift (MISR) registers, and programs for local test vector compression and decompression [2]. In [1] an embedded AMS test controller is proposed which makes use of the IEEE 1149.4 standard [8] and utilizes the embedded memory to support test operations.…”