A bridging model for multi-core computing

Valiant, Leslie G.

doi:10.1016/j.jcss.2010.06.012

Cited by 135 publications

(130 citation statements)

References 31 publications

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“…1 shows, for example, the memory hierarchy for the Xeon based Nehalem architecture, the current generation of desktop architecture from Intel. Correspondingly there has been significant recent work on parallel cache based locality [1,8,5,19,11,7,4,12,23,9,13]. The work has fallen into two main classes.…”

Section: Introductionmentioning

confidence: 99%

Scheduling irregular parallel computations on hierarchical caches

Blelloch

Fineman

Gibbons

et al. 2011

Proceedings of the Twenty-Third Annual ACM Symposium on Parallelism in Algorithms and Architectures

102

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Making efficient use of cache hierarchies is essential for achieving good performance on multicore and other shared-memory parallel machines. Unfortunately, designing algorithms for complicated cache hierarchies can be difficult and tedious. To address this, recent work has developed high-level models that expose locality in a manner that is oblivious to particular cache or processor organizations, placing the burden of making effective use of a parallel machine on a runtime task scheduler rather than the algorithm designer/programmer. This paper continues this line of work by (i) developing a new model for parallel cache cost, (ii) developing a task scheduler for irregular tasks on cache hierarchies, and (iii) proving that the scheduler assigns tasks to processors in a work-efficient manner (including cache costs) relative to the model. As with many previous models, our model allows algorithms to be analyzed using a single level of cache with parameters M (cache size) and B (cache-line size), and algorithms can be written cache obliviously (with no choices made based on machine parameters). Unlike previous models, our cost Q α (n; M, B), for problem size n, captures costs due to work-space imbalance among tasks, and we prove a lower bound that shows that some sort of penalty is needed to achieve work efficiency. Nevertheless, for many algorithms, Q α () is asymptotically equal to the standard sequential cache cost Q().Our task scheduler is a specific "space-bounded scheduler," which assigns subtasks to caches based on their space usage. Our scheduler extends prior work by efficiently scheduling "irregular" computations with arbitrary work imbalance among parallel subtasks, reflected by the Q α () cost. Moreover, in addition to proving bounds on cache complexity, we also provide a bound on the total running time of an program execution using our scheduler. Specifically, our scheduler executes a program on a homogeneous h-level parallel memory hierarchy having p processors in time O (v h /p) h i=0 Q α (n; M i , B) · C i , where M i is the size of the level-i cache, B is the cache-line size, C i is the cost of level-i cache miss, and v h is an overhead defined in the paper. Ignoring the overhead v h , which may be small (or even constant) when certain side conditions hold, this bound is optimal whenever Q α () matches the sequential cache complexity-at every level of the hierarchy it is dividing the total cache cost by the total number of processors.

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Section: Introductionmentioning

confidence: 99%

Scheduling irregular parallel computations on hierarchical caches

Blelloch

Fineman

Gibbons

et al. 2011

Proceedings of the Twenty-Third Annual ACM Symposium on Parallelism in Algorithms and Architectures

102

View full text Add to dashboard Cite

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“…Hadoop. Pregel is inspired by Bulk Synchronous Parallel [23] computation model where computations on a graph consists of several iterations, also called super-steps. During a super-step, each vertex first receives all the messages which were addressed to it by other vertices in the previous super-step.…”

Section: Related Workmentioning

confidence: 99%

A Block-Based Edge Partitioning for Random Walks Algorithms over Large Social Graphs

Constantin

Mouza

2016

Web Information Systems Engineering – WISE 2016

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Recent results [5,9,25] prove that edge partitioning approaches (also known as vertex-cut) outperform vertex partitioning (edge-cut) approaches for computations on large and skewed graphs like social networks. These vertex-cut approaches generally avoid unbalanced computation due to the power-law degree distribution problem. However, these methods, like evenly random assigning [25] or greedy assignment strategy [9], are generic and do not consider any computation pattern for specific graph algorithm. We propose in this paper a vertex-cut partitioning dedicated to random walks algorithms which takes advantage of graph topological properties. It relies on a blocks approach which captures local communities. Our split and merge algorithms allow to achieve load balancing of the workers and to maintain it dynamically. Our experiments illustrate the benefit of our partitioning since it significantly reduce the communication cost when performing random walks-based algorithms compared with existing approaches.

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“…Recently, Valiant proposed an adaptation of the BSP model over multicore architectures; he called this model Multi-BSP [19]. Multi-BSP incorporates the memory size as an additional parameter.…”

Section: It Is Common To Present the Parameters Of The Bsp Model As Amentioning

confidence: 99%

A Simple BSP-based Model to Predict Execution Time in GPU Applications

Amarís

Cordeiro

Goldman

et al. 2015

2015 IEEE 22nd International Conference on High Performance Computing (HiPC)

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Abstract-Models are useful to represent abstractions of software and hardware processes. The Bulk Synchronous Parallel (BSP) is a bridging model for parallel computation that allows algorithmic analysis of programs on parallel computers using performance modeling. The main idea of BSP model is the treatment of communication and computation as abstractions of a parallel system. Meanwhile, the use of GPU devices are becoming more widespread and they are currently capable of performing efficient parallel computation for applications that can be decomposed on thousands of simple threads. However, few models for predicting application execution time on GPUs have been proposed.In this work we present a simple and intuitive BSP-based model for predicting the CUDA application execution times on GPUs. The model is based on the number of computations and memory accesses of the GPU, with additional information on cache usage obtained from profiling. Scalability, divergence, effect of optimizations and differences of architectures are adjusted by a single parameter. We evaluated our model using two applications and six different boards. We showed by using profile information for a single board, that the model is general enough to predict the execution time of an application with different input sizes and on different boards with the same architecture. Our model predictions were within 0.8 to 1.2 times the measured execution times, which are reasonable for such a simple model. These results indicate that the model is good enough to generalize the predictions for different problem sizes and GPU configurations.

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A bridging model for multi-core computing

Cited by 135 publications

References 31 publications

Scheduling irregular parallel computations on hierarchical caches

Scheduling irregular parallel computations on hierarchical caches

A Block-Based Edge Partitioning for Random Walks Algorithms over Large Social Graphs

A Simple BSP-based Model to Predict Execution Time in GPU Applications

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