A built-in self-reconfigurable scheme for 3D mesh arrays

Takanami, Itsuo; Horita, Tadayoshi

doi:10.1109/ispan.1997.645137

Cited by 5 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using the same assumptions as in [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], all switches and interconnects in an array are assumed to be fault-free. This assumption is justified since the switches and links use much less hardware resources when compared to the PEs and are thus less vulnerable to faults.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…The gray shaded boxes in the figure represent faulty PEs, while other boxes represent the fault-free PEs. Each circle represents a six-port switch for reconfiguration, and there are 15 states for each switch [29], [30], [31], as shown in Fig. 1.…”

Section: D Architecture and Notationsmentioning

confidence: 99%

“…The former replaces faulty PEs using spare ones to obtain a logical array with a guaranteed size, while the latter tries to provide a target array as large as possible. For fault tolerance of 3D processor array, three different redundancy approaches are proposed in [28], [29], [30], however, an array must be discarded if its spare PEs cannot replace all faulty ones. Few works have been reported on 3D degradable processor arrays.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of m 0 Â n 0 Â h 0 from a faulty array of m Â n Â h (m 0 m; n 0 n; h 0 h), such that an original application can still work on the m 0 Â n 0 Â h 0 subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.Index Terms-3D processor array, fault tolerance, maximum logical array, interconnection length, NP-complete problem, algorithm Ç G. Jiang is with the

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

Section: D Architecture and Notationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Fig. 1(a) and (e) show the architecture and switch states of a host array of 2×3×3 in which any adjacent PEs are connected by interconnect links with 6-port switches, and there are 15 states for each switch [14] [15].…”

Section: Preliminariesmentioning

confidence: 99%

“…For the reconfiguration of three-dimensional (3D) mesh array, many kinds of redundancy approaches are proposed [14] [15]. In degradation approach, the latest work [16] proposed three bypass schemes ( -direction, -direction anddirection bypass schemes) and three rerouting schemes ( -plane, -plane and -plane rerouting schemes), followed by a heuristic algorithm, denoted as BGPR, to construct the maximum target array.…”

Section: Introductionmentioning

confidence: 99%

Non-Backtracking Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Jiang

Sun

2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

View full text Add to dashboard Cite

Fast reconfiguration is one of the main challenges in fault tolerant VLSI arrays. In these arrays, there are some invalid processing elements (PEs) that are fault-free but cannot be used to form a target array. These invalid PEs lead to backtracking in reconfiguration. This paper proposes a non-backtracking reconfiguration (NBR) algorithm for three-dimensional degradable VLSI array with faults. The proposed algorithm accelerates the reconfiguration without loss of harvest, by eliminating the backtracking operation that frequently occurs in the existing algorithm (named as BGPR) cited in this paper. Initially, the invalid PEs are identified in the preprocessing for the host array. Then NBR algorithm constructs each logical plane from bottom to top in the host array, and updates the set of the invalid PEs in the host array after a logical plane is constructed. Experimental results show that the NBR algorithm is more scalable than the BGPR algorithm, and thus it can reconfigure large host arrays much faster. In addition, the runtime of NBR algorithm tends to decrease, rather than increase as did in BGPR algorithm, with the increasing fault density.Index Terms-3D VLSI array, reconfiguration, fault tolerant, non-backtracking algorithm.

show abstract

Self-reconfiguration scheme of 3D-mesh arrays

Horiguchi¹,

Numata²

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

View full text Add to dashboard Cite

A built-in self-reconfigurable scheme for 3D mesh arrays

Cited by 5 publications

References 10 publications

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Non-Backtracking Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Self-reconfiguration scheme of 3D-mesh arrays

Contact Info

Product

Resources

About