A bulk-driven differential CMOS schmitt trigger with adjustable hysteresis for ultra-low-voltage operation

Nejati, Ali; Radfar, Sara; Amiri, Parviz; Maghami, Mohammad Hossein

doi:10.1016/j.mejo.2021.105129

Cited by 7 publications

(4 citation statements)

References 20 publications

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“…A. Nejati et al [21] examined FinFET as a temperature nano-sensor according to the type of semiconductor. FinFET temperature sensitivity was simulated for different constituent semiconductor materials (Si, Ge, GaAs, and InAs).…”

Section: Related Workmentioning

confidence: 99%

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

Jabbar

Mahmood

Sultan³

2022

TELKOMNIKA

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Section: Related Workmentioning

confidence: 99%

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

Jabbar

Mahmood

Sultan³

2022

TELKOMNIKA

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“…In these circuits, a combination of three techniques of DTTS, MTSCStack, and NMOS/PMOS bulkdriven differential pair is implemented [23]- [25]. In the bulk-driven approach, the input signals (VIN and reference voltage VREF) are applied to the bulk terminals of transistors NM1 and NM2, whereas the gate terminals of these devices are biased with a VG of 0.5 V. The channel current is modulated by the input signals applied to the bulk terminals.…”

Section: Comparator With Dtts and Mtscstack And Nmos/pmos Bulk-driven Differential Pairmentioning

confidence: 99%

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Mustaffa

2021

IJRES

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Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

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“…The associate editor coordinating the review of this manuscript and approving it for publication was Paolo Crippa . [27], [28], [29]. This is mainly due to the supply voltage reduction trend, which represents a key design technique in the power consumption optimization of electronic systems [30].…”

Section: Introductionmentioning

confidence: 99%

“…The circuit has a tuning range of approximately 110mV , and it consumes 1.38µW with a supply voltage of 0.6V . One year later, a less power consuming (120nW , with supply voltage of 0.4V ) differential ST circuit (0.18µm CMOS process) has been proposed by Nejati et al [29]. In 2021, Fernandes et al analyzed the subthreshold operation of a 3-inverter CMOS Schmitt trigger [25].…”

Section: Introductionmentioning

confidence: 99%

Subthreshold Modeling of a Tunable CMOS Schmitt Trigger

2023

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In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors' geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS 0.35µm CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.INDEX TERMS CMOS, hysteresis, low voltage, Schmitt trigger, subthreshold.

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A bulk-driven differential CMOS schmitt trigger with adjustable hysteresis for ultra-low-voltage operation

Cited by 7 publications

References 20 publications

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Subthreshold Modeling of a Tunable CMOS Schmitt Trigger

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