A bus delay reduction technique considering crosstalk

Hirose, Kei; Yasuura, Hiroto

doi:10.1145/343647.343815

Cited by 78 publications

(29 citation statements)

References 7 publications

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“…In this setup, we use same parameters extracted for Figure 1 and simulate the entire structure by HSpice simulator. It is well known that propagation delay on a particular RC line (center) is the maximum when neighbor lines switch in opposite direction (for three bus structure) and delay is the minimum for switching in the same direction [7]. In contrast, RLC lines exhibit exactly opposite delay trend [9], [10].…”

Section: Model Parametrs Extraction and Simulation Setupmentioning

confidence: 99%

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

Roy

Jha

Chowdhury

2007

2007 14th IEEE International Conference on Electronics, Circuits and Systems

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This paper investigates the impact of signal rise and fall time variations on voltage overshoot and propagation delay in inductive lines for different switching patterns. Equivalent circuit model parameters have been extracted using FastCap and FastHenry field solvers; and results have been obtained by HSpice simulator. Most existing works study the impacts of different switching patterns considering only a constant rise/fall time. However, here it is observed that decreasing rise/fall time alters the inductive behavior under different switching patterns. The investigation in this paper reveals that switching patterns start showing significant impact for a particular range of rise and fall times.

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Section: Model Parametrs Extraction and Simulation Setupmentioning

confidence: 99%

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

Roy

Jha

Chowdhury

2007

2007 14th IEEE International Conference on Electronics, Circuits and Systems

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“…At a higher level of design abstraction, intentionally skewing signal transition timings on adjacent wires has been proposed to reduce the delay effects of crosstalks. This method is only applicable to repeaterenabled communication channels [17].…”

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confidence: 99%

An Efficient Method to Reliable Data Transmission in Network-on-Chips

Patooghy

Tabkhi

Miremadi

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Data transmission in Network-on-Chips (NoCs) is a serious problem due to crosstalk faults happening in adjacent communication links. This paper proposes an efficient flowcontrol method to enhance the reliability of packet transmission in Network-on-Chips. The method investigates the opposite direction transitions appearing between flits of a packet to reorder the flits in the packet. Flits are reordered in a fixed-size window to reduce: 1) the probability of crosstalk occurrence, and 2) the total power consumed for packet delivery. The proposed flow-control method is evaluated by a VHDL-based simulator under different window sizes and various channel widths. Simulation results enable NoC designers to make a trade-off between window size, reliability and power consumption of packet delivery. This method is also compared with other crosstalk tolerant methods in terms of reliability and power consumption. Comparison results confirm that the method is a cost efficient solution to overcome the crosstalk problem.

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“…Increasing line-to-line spacing and non-uniform wire placement [5]- [8] were proposed to decrease the physical coupling capacitance between bus lines. Bus ordering [10], bus swizzling [9], repeater staggering [11] and skewing signal transition timing of adjacent lines [12] were introduced to reduce the effective coupling capacitance.…”

Section: Introductionmentioning

confidence: 99%

Serial-link bus: a low-power on-chip bus architecture

Ghoneima¹,

Ismail²,

Khellah³

et al.

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus CB architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus SLB, transforms an n-bit conventional parallel-line bus into an n/mline (serial-link) bus. The advantage of serial-link buses is that they have fewer lines, and if the bus width is kept the same, seriallink buses will have larger line width and spacing. Increasing the line width has a twofold reduction effect on the line resistance, as the resistivity of sub-100nm wires significantly drops as the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m opt exists that minimizes the bus energy dissipation and maximizes the bus throughput-per-unit area. The optimum degree of multiplexing for maximum throughput-perunit-area and for minimum energy dissipation for the 25-130nm technologies was determined in this paper. HSPICE simulations show that, for the same throughput-per-unit-area as conventional parallel-line buses, the serial-link bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit bus implemented in an intermediate metal layer of a 50nm technology and a reduction of 52.7% is projected for the 25nm technology.

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A bus delay reduction technique considering crosstalk

Cited by 78 publications

References 7 publications

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

An Efficient Method to Reliable Data Transmission in Network-on-Chips

Serial-link bus: a low-power on-chip bus architecture

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