A cache-defect-aware code placement algorithm for improving the performance of processors

Abstract

Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that faultfree sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed [3][4][5]. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.I.

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation

“…Shirvani et al [21] describe a programmable address decoder that redirects accesses to slow/faulty cache lines to other lines in the same cache-set. Another simpler technique to bypass slow cache lines [10] uses an unused combination of flag bits to mark the cache-line as faulty and to eliminate it from normal operation of the cache. These are not applicable to general SRAM memories other than caches.…”

“…In cache memories, several previous works address improving timing-yield in presence of process variation by proposing process-tolerant cache architectures [1], [21] and codeplacement compiler techniques [10], but they actually reduce the useful capacity of the cache by marking and avoiding to use tooslow cache lines. Although [10] provides a solution to mitigate the performance impact, it demands a per-chip different binary executable. Other highly-cited works exist to reduce cache static power [2][12] [6], but they do not consider process-variation.…”

“…Row/column redundancy has long been used to repair faults in RAM memories [13] and has more recently become inevitable in high-density SRAM memories to obtain acceptable manufacturing yield [13]. In cache memories, several previous works address improving timing-yield in presence of process variation by proposing process-tolerant cache architectures [1], [21] and codeplacement compiler techniques [10], but they actually reduce the useful capacity of the cache by marking and avoiding to use tooslow cache lines. Although [10] provides a solution to mitigate the performance impact, it demands a per-chip different binary executable.…”

An analytical model for the calculation of the Expected Miss Ratio in faulty caches

“…However, the study still relies on the execution of random maps which are generated by means of Monte Carlo method. Finally, there are several other studies [1], [21], [20], [10], [11] looking into the impact of faults over caches using random maps.…”

“…Previous block disabling-based studies (such as [22], [19], [21], [13], [12], [10], [20], [11]) rely on the use of an arbitrary number (small or large) of random fault-maps. Each random fault-map indicates faulty cache cell locations and determines the disabled faulty cache blocks.…”