A cache memory with unit tile and line accessibility

Wang, Baokang; Fukazawa, Yoshiaki; Kondo, Takeshi; Sasaki, Takahiro

doi:10.1109/hpcsim.2016.7568425

Cited by 3 publications

(11 citation statements)

References 16 publications

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“…Our work is similar to [9]- [11] in that a clustered tile address layout is presented. Our work differs from [9]- [11] in that the tiled map is configurable.…”

Section: Related Workmentioning

confidence: 99%

“…In [10], the 4D tile format is presented where a dimension is fixed. In [11], a cache memory mapping with both unit tile and unit line accessibility based on the 4-level Z-order tiling layout is presented. Our work is similar to [9]- [11] in that a clustered tile address layout is presented.…”

Section: Related Workmentioning

confidence: 99%

“…In [11], a cache memory mapping with both unit tile and unit line accessibility based on the 4-level Z-order tiling layout is presented. Our work is similar to [9]- [11] in that a clustered tile address layout is presented. Our work differs from [9]- [11] in that the tiled map is configurable.…”

Section: Related Workmentioning

confidence: 99%

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Virtual Address Remapping with Configurable Tiles in Image Processing Applications

Hur

2020

IEICE Trans. Inf. & Syst.

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The conventional linear or tiled address maps can degrade performance and memory utilization when traffic patterns are not matched with an underlying address map. The address map is usually fixed at design time. Accordingly, it is difficult to adapt to given applications. Modern embedded system usually accommodates memory management units (MMUs). As a result, depending on virtual address patterns, the system can suffer from performance overheads due to page table walks. To alleviate this performance overhead, we propose to cluster and rearrange tiles to construct an MMU-aware configurable address map. To construct the clustered tiled map, the generic tile number remapping algorithm is presented. In the presented scheme, an address map is configured based on the adaptive dimensioning algorithm. Considering image processing applications, a design, an analysis, an implementation, and simulations are conducted. The results indicate the proposed method can improve the performance and the memory utilization with moderate hardware costs.

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“…Our work is similar to [9]- [11] in that a clustered tile address layout is presented. Our work differs from [9]- [11] in that the tiled map is configurable.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Virtual Address Remapping with Configurable Tiles in Image Processing Applications

Hur

2020

IEICE Trans. Inf. & Syst.

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“…This tile/line dual accessibility is based on a multi‐bank memory array structure supporting skewed array storage schemes to reduce the excessive transfer of data accesses with 2‐D spatial reference locality. In Wang et al,() we introduced the basic concepts of a 2‐way set associative cache (8 Kbytes, 32‐byte cache line) with 8×4 byte tile and 32‐byte line accessibility for 2‐D data processing. Compared with our previous works,() the most outstanding specific contributions of the present study are highlighted below: We propose a new 8‐way set associative cache (32 Kbytes, 64‐byte cache line) with an 8×8 byte‐sized tile and 64‐byte‐sized line accessibility.…”

Section: Introductionmentioning

confidence: 99%

“…In Wang et al,() we introduced the basic concepts of a 2‐way set associative cache (8 Kbytes, 32‐byte cache line) with 8×4 byte tile and 32‐byte line accessibility for 2‐D data processing. Compared with our previous works,() the most outstanding specific contributions of the present study are highlighted below: We propose a new 8‐way set associative cache (32 Kbytes, 64‐byte cache line) with an 8×8 byte‐sized tile and 64‐byte‐sized line accessibility. Parallel aligned/unaligned tile and line access corresponding to parallel data access in the column and row directions can improve the throughput with a low latency overhead of memory. To reduce the hardware overhead of the proposed cache, we propose a tag memory reduction method that replaces multiple tiles with an aligned tile set (RATS) in the cache.…”

Section: Introductionmentioning

confidence: 99%

Tile/line access cache memory based on a multi‐level Z‐order tiling data layout

Wang

Fukazawa

Kondo

et al. 2017

Concurrency and Computation

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Summary Ineffective column‐directional cache memory access has become a bottleneck for efficient two‐dimensional (2‐D) data processing utilizing extended single instruction multiple data (SIMD) instructions. To solve this problem, we propose a cache memory with tile (column and row directions) and line (row direction) accessibility for efficient 2‐D data processing. 2‐D data access to the proposed cache memory is enabled via a hardware‐based multi‐mode address translation unit that eliminates the overhead of software‐based address calculation. To reduce the hardware overhead of the proposed cache, we propose a tag memory reduction method that replaces multiple tiles with an aligned tile set (RATS) in the cache. To verify the feasibility of the proposed cache, an LSI layout of a SIMD‐based general purpose‐oriented datapath embedding the proposed cache is designed in a 2.5×5 mm2 area using 0.18‐μm CMOS technology. Under a 3.9‐ns clock period (250 MHz), the read latency is limited to 3 clock cycles, which is the same as that for the conventional cache memory. Using the RATS method, the entire hardware overhead of the proposed cache is reduced to only 7% of that required for a conventional cache. In addition, simulation results for the proposed cache indicate a considerable reduction of L1 and L2 cache confliction misses compared with a conventional cache in power‐of‐two matrix size due to the column‐directional address stride being sufficiently smaller than page size. Therefore, the proposed cache provides efficient column‐directional parallel access as same as row‐directional parallel access so that it enables efficient SIMD operation requiring no transposition in matrix multiplication (MM). For LU decomposition (LUD), the proposed cache can provide almost the same performance to the column‐major–based LUD program as that to the row‐major–based LUD program. These results show that the proposed cache does not restrict our freedom in selecting either row‐ or column‐major order coding.

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Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Wang

2019

Mathematical Problems in Engineering

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In recent years, the increasing disparity between the data access speed of cache and processing speeds of processors has caused a major bottleneck in achieving high-performance 2-dimensional (2D) data processing, such as that in scientific computing and image processing. To solve this problem, this paper proposes new dual unit tile/line access cache memory based on a hierarchical hybrid Z-ordering data layout and multibank cache organization supporting skewed storage schemes. The proposed layout improves 2D data locality and reduces L1 cache misses and Translation Lookaside Buffer (TLB) misses efficiently and it is transformed from conventional raster layout by a simple hardware-based address translation unit. In addition, we proposed an aligned tile set replacement algorithm (ATSRA) for reduction of the hardware overhead in the tag memory of the proposed cache. Simulation results using Matrix Multiplication (MM) illustrated that the proposed cache with parallel unit tile/line accessibility can reduce both the L1 cache and TLB misses considerably as compared with conventional raster layout and Z-Morton order layout. The number of parallel load instructions for parallel unit tile/line access was reduced to only about one-fourth of the conventional load instruction. The execution time for parallel load instruction was reduced to about one-third of that required for conventional load instruction. By using 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, we combined the proposed cache with a SIMD-based data path and designed a 5 × 5 mm2 Large-Scale Integration (LSI) chip. The entire hardware overhead of the proposed ATSRA-cache was reduced to only 105% of that required for a conventional cache by using the ATSRA method.

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A cache memory with unit tile and line accessibility

Cited by 3 publications

References 16 publications

Virtual Address Remapping with Configurable Tiles in Image Processing Applications

Virtual Address Remapping with Configurable Tiles in Image Processing Applications

Tile/line access cache memory based on a multi‐level Z‐order tiling data layout

Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

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