A CAD system for the design of field programmable gate arrays

Hill, Dwight D.

doi:10.1145/127601.127662

Cited by 27 publications

(8 citation statements)

References 8 publications

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“…The FPGA routing is a highly complex combinatorial optimization problem, and thus it is usually done by iterative rip-up and reroute of signals. The success of routing is dependent not just on the choice of which nets to reroute, but also on the order in which rerouting is done as shown in traditional rip-up and reroute methods [10,11]. The negotiation-based FPGA router successfully relieves the signal ordering problem and provides a systematic rip-up and reroute capability [12].…”

Section: Conventional Routing Problemsmentioning

confidence: 99%

Networked architecture for hybrid electrical energy storage systems

Kim

Park

Chang

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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A hybrid electrical energy storage (HEES) system that consists of multiple, heterogeneous electrical energy storage (EES) elements is a promising solution to achieve a cost-effective EES system because no storage element has ideal characteristics. The state-ofthe-art HEES systems are based on a shared-bus charge transfer interconnect (CTI) architecture. Consequently, they are quite limited in scalability which is a function of the number of EES banks. This paper is the first introduction of a HEES system based on a networked CTI architecture, which is highly scalable and is capable of accommodating multiple, concurrent charge transfers. The paper starts by presenting a router architecture for the networked CTI and an effective on-line routing algorithm for multiple charge transfers. In the proposed algorithm, negotiated congestion (NC) routing for multiple charge transfers is performed and any lack of routing resources is addressed by merging two or more charge transfers while maximizing the overall energy efficiency by setting the optimal voltage level for the shared CTI. Examples of the proposed networked CTI are presented and the efficacy of the routing algorithm is demonstrated on a mesh-grid networked CTI.

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Section: Conventional Routing Problemsmentioning

confidence: 99%

Networked architecture for hybrid electrical energy storage systems

Kim

Park

Chang

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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“…While rip-up and retry based routing for designs routed from scratch has been explored for nearly forty years [9] [16], only recently has significant interest been given to recovering previously-working route configurations. In [12], a re-route approach for FPGAs was described that re-routes nets following logic block movement.…”

Section: Related Workmentioning

confidence: 99%

Tolerating operational faults in cluster-based FPGAs

Lakamraju

Tessier

2000

Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays

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in recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults. Our preferred approach to fault recovery takes advantage of device routing hierarchy in architectural families such as Xilinx Virtex [2] and Alters Apex [3] to quickly swap unused logic and routing resources in place of faulty ones within logic clusters. These algorithms allow for straightforward implementation within a local fault-tolerant system without the need to access a remote processing location. If initial recovery attempts through localized swapping fail, an incremental router based on the widely-used PathFinder maze routing algorithm [10] can be applied remotely in an attempt to form connections between newly-allocated logic and interconnect based on the history of the initial design route.

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“…[Hill91] uses a breadthfirst search while performing routes in random order and a "blame factor" is introduced to decide what routes need to be ripped up when a connection is unrealized. [Brown92] uses a global router to assign connections so that channel densities are balanced; a detailed router generates families of explicit paths within channels to resolve congestion.…”

Section: Introductionmentioning

confidence: 99%

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

McMurchie

Ebeling

1995

Third International ACM Symposium on Field-Programmable Gate Arrays

369

327

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Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.

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A CAD system for the design of field programmable gate arrays

Cited by 27 publications

References 8 publications

Networked architecture for hybrid electrical energy storage systems

Networked architecture for hybrid electrical energy storage systems

Tolerating operational faults in cluster-based FPGAs

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

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