A capacitance solver for incremental variation-aware extraction

Abstract

Abstract-Lithographic limitations and manufacturing uncertainties are resulting in fabricated shapes on wafer that are topologically equivalent, but geometrically different from the corresponding drawn shapes. While first-order sensitivity information can measure the change in pattern parasitics when the shape variations are small, there is still a need for a high-order algorithm that can extract parasitic variations incrementally in the presence of a large number of simultaneous shape variations. This paper proposes such an algorithm based on the wellknown method of floating random walk (FRW). Specifically, we formalize the notion of random path sharing between several conductors undergoing shape perturbations and use it as a basis of a fast capacitance sensitivity extraction algorithm and a fast incremental variational capacitance extraction algorithm. The efficiency of these algorithms is further improved with a novel FRW method for dealing with layered media. Our numerical examples show a 10X speed up with respect to the boundaryelement method adjoint or finite-difference sensitivity extraction, and more than 560X speed up with respect to a non-incremental FRW method for a high-order variational extraction.

Stochastic extraction for SoC and SiP interconnect with variability

“…Different strategies have been proposed in the literature to address such challenge, such as parallelization, Krylov subspace recycling [12], [13], stochastic model order reduction [14], [15], [11], [16] and path recycling of floating random walk (PR-FRW) [3] (exclusively for capacitance and resistance extraction).…”

“…Such methods are discretization-free and do not rely on assembling or solving any linear systems of equations [1], [2]. Such methods will not be addressed in this paper and the reader is referred to [3] for a stochastic version of the floating random walk algorithm which uses path recycling (PR-FRW) to accelerate any samplingbased (i.e. non-intrusive) stochastic capacitance solver.…”

Parameterized Model Order Reduction

“…Novel extraction methodologies can efficiently generate such sensitivity information [5,26]. A nice feature of this representation is that this explicit parameter dependence allows to obtain a reduced, yet similar representation when a projection scheme is applied Some questions may be raised about the order neccessary for an accurate representation of the parametric model.…”

Efficient Space Management Techniques for Large-Scale Interconnect Capacitance Extraction With Floating Random Walks

“…With parallel computing techniques, they have been applied to the block-or chip-level extraction task in the sign-off verification of very large scale integration (VLSI) circuits. Recently, a general FRW algorithm [3] and a hierarchical FRW algorithm [4] were proposed to deal with arbitrary dielectric configuration and for a fabric-aware extraction problem, respectively. In 2013, an FRW algorithm [5] was proposed for the interconnect structure with multilayered dielectrics, where the cross-interface transition probability and weight value are precharacterized for a given process technology.…”