A case study in using two-level control stores

Abstract

A two-level control store can reduce storage requirements of microprograms without affecting microprogrammability, which is important for a processor programmed directly in microcode. This paper presents a case study investigating how to use a two-level control store effectively. The study is based on Warp cell, a high-performance, microprogrammable processor used in a systolic array computer called Warp. Warp cell is programmed directly in microcode by an optimizing compiler and uses wide horizontal microinstructions with over 200 bits.Two methods which can increase the effectiveness of using a two-level control store have been considered. First, control store configuration can be adjusted so that the storage of an instruction can be partitioned among microstore and one or more nanostores to maximize storage efficiency. Second, it is possible to increase storage reduction of microprograms by exploiting insignificant and symmetric fields in instructions in mapping microprograms to the control store. It has been found that the average storage reduction for Warp cell programs can be increased from 41% in a straightforward two-level control store implementation to 72% by using these methods.

Hierarchical Instruction Register Organization

“…Microcode and microprogramming [1], [13] have a long history as techniques to compress instruction streams. Two-level control stores for the microprogammable Warp cell were proposed to reduce code storage pressure [9]. The Warp structure resembles the indirect indexing of the IRF architecture proposed here, with their microstore and nanostore operating much as the CIM and IRFs.…”

Algoritmos para compressão de microcodigo

“…Menzilcioglu [97] investigou a utilização de microcódigo em dois níveis para aumentar a capacidade de armazenamento do processador Warp [8]. O autor observou que alguns campos do microcódigo apresentavam mais regularidade do que outros e utilizou diversas nanoROMs para agrupar diferentes partes do microcódigo.…”

“…Zhao e Papachristou [136] propuseram uma organização do microcódigo em memórias distribuídas muito similar ao modelo com mais de uma nanoROM utilizado por Menzilcioglu [97] (Figura 2.10). No modelo de Zhao e Papachristou, a µROM e a nanoROM são chamadas de index memory e microcode memory module, respectivamente.…”

“…A organização do microcódigo em dois níveis foi explorada em diversos trabalhos com pequenas variações em torno da microarquitetura do descompressor [25,46,65,97,114,119,136]. Apesar da semelhança das estruturas e da organização do descompressor, os termos usados para definir os componentes da microarquitetura, como a µROM e a nanoROM, diferem na maioria desses trabalhos.…”