A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors

Heinz, Carsten; Lavan, Yannick; Hofmann, Jaco; Koch, Andreas

doi:10.1109/reconfig48160.2019.8994796

Cited by 39 publications

(25 citation statements)

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“…The addition of PE-local memories draws from scratchpad approaches (cf. [1,19,76]) and was essential for later work, e.g., an evaluation and survey of FPGA-compatible RISC-V cores in [27].…”

Section: Recent Workmentioning

confidence: 99%

“…TaPaSCo provides a number of features that facilitate this task, e.g., the support for local memories directly attached to the processing elements that can be used for instruction and low-latency data memory for RISC-V softcores. In [27], a catalog of open-source RISC-V cores was integrated with TaPaSCo and evaluated with regard to suitability for FPGAs and benchmark performance. More details on how these softcores were integrated with TaPaSCo can be found in the next section.…”

Section: Softcoresmentioning

confidence: 99%

“…As a result, development cycles are longer than in "traditional" software engineering. To combine both worlds and enable fast prototyping with shorter iterations, RISC-V softcore processors are introduced to TaPaSCo [27]. With this setup, the synthesis run is required only once.…”

Section: Case Study: Risc-v-based Many-core Architecturementioning

confidence: 99%

“…To allow TaPaSCo to automatically construct the SoC design, the first step is to design a TaPaSCo-compatible PE. One way to do this is shown in [27], which describes the process to wrap seven different open-source RISC-V cores for compatibility with TaPaSCo. To this end, the design is wrapped into the T-shape, previously discussed in Section 3.1, as follows:…”

Section: Risc-v Processing Elementsmentioning

confidence: 99%

“…The ID identifies the functionality of a PE, e.g., the abstract algorithm. Different implementations or algorithms performing the same computation will usually share the Figure 6 RISC-V processing element: RVController provides an AXI4Lite slave interface for TaPaSCo; BRAM is accessible via an AXI4 controller from the RISC-V, as well as from the host (adapted from [27]). same type ID.…”

Section: Risc-v Processing Elementsmentioning

confidence: 99%

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The TaPaSCo Open-Source Toolflow

Heinz

Hofmann

Korinth

et al. 2021

J Sign Process Syst

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The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

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Section: Recent Workmentioning

confidence: 99%

Section: Softcoresmentioning

confidence: 99%

Section: Case Study: Risc-v-based Many-core Architecturementioning

confidence: 99%

Section: Risc-v Processing Elementsmentioning

confidence: 99%

Section: Risc-v Processing Elementsmentioning

confidence: 99%

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