A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography

Chien, Hsi-An; Han, Szu-Yuan; Chen, Ye‐Hong; Wang, Ting-Chi

doi:10.1145/2717764.2717768

Cited by 15 publications

(5 citation statements)

References 11 publications

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“…Mandrel/spacer engineering based self-aligned multiple patterning (SAMP [10][11][12][13][14][15][16][17][18][19]) techniques have been applied to fabricate advanced logic/DRAM critical layers. Various SAMP schemes, e.g., double (SADP), triple (SATP), quadruple (SAQP), sextuple (SASP), octuple (SAOP) techniques have been reported.…”

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

“…However, its scalability is limited due to the significantly increased process complexity and mask number when extended to more aggressive density-multiplication scenarios. In general, self-aligned quadruple/octuple patterning (SAQP/SAOP) is more capable of increasing the pattern density of 1-D features; while self-aligned triple/sextuple patterning (SATP/SASP) is beneficial to reducing the process complexity by allowing more CD/design freedom and requiring fewer masks [10][11][12][13][14][15][16][17][18][19]. Table 1.…”

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

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Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layerdivision realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.

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Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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show abstract

“…Several follow-up researches propose algorithms to solve the problem by trading off performance and runtime [65][66][67]. For row based layout structure in which rows are assumed to be separated by wide power grids, the layout decomposition problem can be solved in polynomial time [68][69][70][71].…”

Section: Mpl Layout Decompositionmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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“…Further study has been done for constrained pattern assignment where the color solutions for the same type of standard cells are required to be the same [15]. By reducing the graph size and parallelization, decomposers are capable of computing solutions in even shorter time [16,17].…”

Section: Figure 3: Vector Based Color Representationsmentioning

confidence: 99%

Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

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A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography

Cited by 15 publications

References 11 publications

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Design for manufacturability and reliability in extreme-scaling VLSI

Pushing multiple patterning in sub-10nm

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