A cellular computing architecture for parallel memristive stateful logic

Lehtonen, Eero; Tissari, Jari; Poikonen, Jussi; Laiho, Mika; Koskinen, Lauri

doi:10.1016/j.mejo.2014.09.005

Cited by 24 publications

(36 citation statements)

References 14 publications

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“…The topic of this paper, namely memristive logic computing in large crossbar architectures has previously been considered in [3], [4], [6], [18]. Building on the ideas presented in these papers, we show in this paper how recursive, logarithmic-time algorithms can be efficiently realized in a memristive logic array.…”

Section: A Related Workmentioning

confidence: 92%

“…In memristor ratioed logic [15], antiserially connected memristors are used to dynamically switch into a state that corresponds to a given logical function of the input voltages. In literature there exists also a variety of different logic computation approaches that use memristors as [3]. A memristor is formed in each crossing of horizontal and vertical nanowires.…”

Section: A Related Workmentioning

confidence: 99%

“…In the following we describe the main functionality of the memristive logic array, which was originally presented in [3]. The MLA allows to perform vectorized parallel memory and logic operations, where data is represented by the resistive states-or memristances-of bistate rectifying memristors.…”

Section: A the Memristive Logic Arraymentioning

confidence: 99%

“…In [3] we proposed a computing-in-memory architecture for massively parallel memristive stateful logic called the memristive logic array (MLA). This architecture consists of multiple small memristive crossbars-for example, formed of eight vertical and eight horizontal nanowires with a memristor at each crossing of the nanowires-interfaced with CMOS cells used for controlling and restoring the voltage signals driven on the nanowires.…”

Section: Introductionmentioning

confidence: 99%

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Recursive Algorithms in Memristive Logic Arrays

Lehtonen

Poikonen

Tissari

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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In memristive stateful logic memristors store logic values as their memristance states and perform logical operations on them. This form of logic has been studied intensively since it was first empirically demonstrated in the work of Borghetti et al., 2010. It has been previously noted that substantial parallelism in stateful computation is required to make this form of logic competetive with conventional logic computing paradigms. In this work we show how a certain class of vectorized recursive algorithms can be computed in a semiconductor/memristor hybrid array structure. This class of algorithms allows efficient computation of many practically important vector operations; examples considered in this paper include the binary sum of vectors, the parity of a vector, and the Hamming weight of a vector. We present theoretical analysis of the time and space complexity of this class of operations, and show examples of this computing method using circuit-level simulations. We also discuss possible applications of these operations in massively parallel memristive array computing.

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Section: A Related Workmentioning

confidence: 92%

Section: A Related Workmentioning

confidence: 99%

Section: A the Memristive Logic Arraymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Recursive Algorithms in Memristive Logic Arrays

Lehtonen

Poikonen

Tissari

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…Nevertheless, mostly owing to the fact that memristor device technology is still at an early stage, such papers have primarily focused on the digital logic realization procedure, logic gate implementation, and/or the device-level requirements, and almost all of them have omitted (or left for future research) the study of the underlying ReRAM organization, the target circuit architecture, and the impact of the driving circuitry. Further research is necessary at the circuit and/or architecture level to make logic computations as parallel as possible and thus enable practical application [21], [22]. It would be particularly interesting to see whether and how such logic design approaches could practically fit in compact memristive storage circuit architectures, exploiting the nonvolatility of memristors in normal power-off (and thus more energy efficient) logic-in-memory circuits.…”

Section: Introductionmentioning

confidence: 99%

Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

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Aquesta és una còpia de la versió draft d'un article publicat a IEEE transactions on nanotechnologyhttp://hdl.handle.net/2117/104473 Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. DOI: 10.1109/TNANO.2017 © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic functions.

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Artificial Skin Perception

et al. 2020

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interact with the world. This inspires scientists and engineers to develop flexible and stretchable electronic devices or systems to emulate the functionality of the human skin, known as electronic skin (e-skin). Recently, tremendous efforts have been made in the development of e-skin from materials innovation to structural designs, which concentrate on the improvement of sensing capability (i.e., stretchability, sensitivity, long-term monitoring, etc.), user-friendly detection mode (i.e., noninvasive, inflammation-free, gaspermeable, implantable, etc.), systemlevel integration (i.e., data transmission, power supply, etc.), and the realization of new functions (i.e., self-healing). [5][6][7] However, as one of the essential elements to mimic human intelligence, the functionality of perception, that is, interpretation of acquired sensory data, is still lacking in most e-skin systems. Implementing the perception functionality in a flexible and stretchable sensing system, referred to as artificial skin perception is vital to realizing an authentically intelligent artificial skin, with capabilities beyond human skin (Figure 1b). Coupled with sensing, feedback, and other technologies (Figure 1c), artificial skin perception will significantly accelerate the development of next-generation soft robotics, where a low-latency and energy-efficient data processing module is required to enable fast adaptation to dynamic environments.Currently, perception processes of most e-skin systems take place in centralized processing units, that is, computers or servers in the cloud, located far away from the sensing systems where sensory signals are generated. These sensory signals, usually time-serial, unstructured, and redundant, need to be continually sent to an external processing end. As a result, there will be a tremendous volume of data movements between the sensing end and the processing end, leading to huge energy consumption. [8,9] Moreover, the frequent and continual exchange of data causes a serious burden to data communication due to the limited bandwidth of communication channels in current sensing systems, especially when a large number of sensors are mounted on the large-area sensing system. [9][10][11] This leads to a notorious latency problem, known as a time delay in response for data communication. [9] The latency issue severely hinders the development of ultrafast responsive and delaysensitive intelligent systems, such as advanced robotics and Skin is the largest organ, with the functionalities of protection, regulation, and sensation. The emulation of human skin via flexible and stretchable electronics gives rise to electronic skin (e-skin), which has realized artificial sensation and other functions that cannot be achieved by conventional electronics. To date, tremendous progress has been made in data acquisition and transmission for e-skin systems, while the implementation of perception within systems, that is, sensory data processing, is still in its infancy. Integrating the perception functionality into a flex...

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A cellular computing architecture for parallel memristive stateful logic

Cited by 24 publications

References 14 publications

Recursive Algorithms in Memristive Logic Arrays

Recursive Algorithms in Memristive Logic Arrays

Crossbar-Based Memristive Logic-in-Memory Architecture

Artificial Skin Perception

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