Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis, Georgios; Vourkas, Ioannis; Abusleme, Angel; Sirakoulis, Georgios Ch.; Rubio, Antonio

doi:10.1109/tnano.2017.2691713

Cited by 66 publications

(29 citation statements)

References 43 publications

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“…However, most such relevant works omit crucial factors such as variability (both cycle-to-cycle and device-to-device) and endurance of memristors; being the latter a major limitation to be considered if frequent switching is necessary during computations. For instance, recently Papandroulidakis et al [21] suggested using different T memristor technology for memory and computing tasks to address endurance issues. Likewise, another logic scheme called Scouting Logic [22] was proposed to alleviate the endurance requirement while executing logic operations by just sensing the memristor state, even though this scheme eventually suffers from device variability.…”

Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycleto-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and complex logic functions.

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Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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“…Moreover, all memristive based logic/computational circuits, i.e. computation of Boolean functions in memristor-only circuits [49] as well as logic computation parallelism with memristors [48] would be examined as feasible promising in-memory computing nano-architectures. As an alternative novel analog computing concepts utilizing massively-parallel computing architectures, enabled by networks of memristors could be also equally considered [74].…”

Section: Computing Concretementioning

confidence: 99%

On Buildings that Compute. A Proposal

Adamatzky

Szaciłowski

Przyczyna

et al. 2019

From Astrophysics to Unconventional Computation

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We present ideas aimed at bringing revolutionary changes on architectures and buildings of tomorrow by radically advancing the technology for the building material concrete and hence building components. We propose that by using nanotechnology we could embed computation and sensing directly into the material used for construction. Intelligent concrete blocks and panels advanced with stimuli-responsive smart paints are the core of the proposed architecture. In particular, the photo-responsive paint would sense the buildings internal and external environment while the nano-materialconcrete composite material would be capable of sensing the building environment and implement massive-parallel information processing resulting in distributed decision making. A calibration of the proposed materials with in-materio suitable computational methods and corresponding building in-formation modelling, computer-aided design and digital manufacturing tools could be achieved via models and prototypes of information processing at nano-level. The emergent technology sees a building as high-level massiveparallel computer -assembled of computing concrete blocks. Based on the generic principles of neuromorphic computation and reservoir computing we envisage a single building or an urban quarter to turn into a large-scale sensing substrate. It could behave as a universal computer, collecting and processing environmental information in situ enabling appropriate data fusion. The broad range of spatio-temporal effects include infrastructural and human mobility, energy, bio-diversity, digital activity, urban management, art and socializing, robustness with regard to damage and noise or real-time monitoring of environmental changes. The proposed intelligent architectures will increase sustainability and viability in digitised urban environments by decreasing information transfer bandwidth by e.g, utilising 5G networks. The emergence of socio-cultural effect will create a cybernetic relationship with our dwellings and cities.

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“…[10][11][12][13] Recent studies have identified various useful and efficient stateful gates for better computing efficiency, and as a result, stateful logic technology has advanced significantly. [14][15][16][17][18][19][20][21][22][23][24] Such various gates are possible by simultaneously applying designed operating voltages on the multiple cells. In general, the word lines of input cells and output cells are biased to a conditioning voltage (V COND ) and programming voltages (V PGM ), respectively.…”

Section: Introductionmentioning

confidence: 99%

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Kim

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic allows complete in‐memory computing and is considered to be a next‐generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near‐memory error correction method for a typical bipolar‐type memristor stateful logic system is proposed. An error correction principles using a HfO2‐based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one‐bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.

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Crossbar-Based Memristive Logic-in-Memory Architecture

Cited by 66 publications

References 43 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

On Buildings that Compute. A Proposal

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

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