A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

In, Jae Hyun; Kim, Young Seok; Song, Hanchan; Kim, Gwang Min; An, Jangho; Jeon, Jae Ho; Kim, Kyung Min

doi:10.1002/aisy.202000081

Cited by 13 publications

(8 citation statements)

References 42 publications

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“…A stateful operation is evaluated not only by the correct logical result, but also the stability of the inputs. This is not always trivial, as reported by previous RRAM works 12,13,15,35 . Results of 50 cycles of: (a) NOR, (b) IMPLY, (c) OR, and (d) NIMP logic gates are shown in Fig.…”

Section: Experimental Results Of the Proposed Logic Gatesmentioning

confidence: 66%

“…Prior studies on stateful logic mostly focused on bipolar RRAM devices [6][7][8][9][10][11][12][13] , which still suffer from reliability and variability issues 14,15 and are unavailable commercially in large scale. Phase-change memory (PCM) is a more mature resistive technology that offers fast operation speed, low power, good reliability and high density integration, while being already used commercially [16][17][18][19] , e.g., in the Intel Optane technology 20 .…”

Section: Introductionmentioning

confidence: 99%

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Crossbar-Compatible Stateful Logic Using Phase Change Memory

Hoffer¹,

Wainstein²,

Neumann³

et al. 2021

Preprint

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Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. This has been previously demonstrated using several resistive memory types, but not with commercially available phase-change memory (PCM). Here we present the first implementation of stateful logic using PCM. We experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials and crossbar-compatible structures. Our stateful logic gates form a functionally complete set, which enables sequential execution of any logic function within the memory and paves the way to PCM-based digital processing-in-memory systems.

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Section: Experimental Results Of the Proposed Logic Gatesmentioning

confidence: 66%

Section: Introductionmentioning

confidence: 99%

Crossbar-Compatible Stateful Logic Using Phase Change Memory

Hoffer¹,

Wainstein²,

Neumann³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…A stateful operation is evaluated not only by the correct logical result, but also the stability of the inputs. This is not always trivial, as reported by previous RRAM works [23], [24], [27], [53]. Results of 50 iterations for: (a) NOR, (b) IMPLY, (c) OR, and (d) NIMP logic gates are shown in Fig.…”

Section: Experimental Demonstrationmentioning

confidence: 54%

“…Prior studies on stateful logic mostly focused on bipolar RRAM devices [16]- [26], which still suffer from reliability and variability issues [7], [27] and are unavailable commercially in large scale. PCM is a more mature resistive technology that offers fast operation speed, low power, good reliability, and high density integration, while being already used commercially [6], [28]- [30], e.g., in the Intel Optane technology [31].…”

mentioning

confidence: 99%

Stateful Logic Using Phase Change Memory

Hoffer

Wainstein

Neumann

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly by resistive RAM (RRAM). Here we present a new method to design stateful logic using a different resistive memoryphase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanism and functionality of PCM compared to RRAM. Since the proposed stateful logic form a functionally complete set, these gates enable sequential execution of any logic function within the memory, paving the way to PCM-based digital processing-in-memory systems.Index Terms-phase-change-memory (PCM), processing-inmemory (PIM), stateful-logic I. INTRODUCTIONF OR the last 75 years, computers have been typically designed in the von Neumann architecture, which separates the memory from the processing units. While their programming model is simple, incessant data movement limits system performance because memory access time is often substantially longer than the computing time. This bottleneck has worsened over the years since CPU speed has improved more than memory speed and bandwidth (the so-called 'memory wall') [1]. One attractive approach to deal with this problem is processing-in-memory (PIM), which suggests adding computation capabilities to the memory. PIM reduces the need for costly (in terms of processing-speed, bandwidth, and energy) chip-to-chip transfers, thus yielding higher performance and energy efficiency [2].An increasing number of applications from highperformance computing (HPC) to databases, data analytics and deep neural networks require higher memory capacity to meet the needs of workloads with large data sets. DRAM scaling has slowed down in the last years, and it has become Manuscript

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“…Based on these two reinforced logic gates, we design a 1-bit full adder, which only need 6 steps and 14 memristors, but has 100% correct rate. It possesses more advantages in delay, area and accuracy than the reported 1-bit full adders [4,7,8].…”

Section: Introductionmentioning

confidence: 99%

Margin‐based reliability reinforcement method for stateful logic

Wang

et al. 2022

Electronics Letters

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The memristive stateful logic can realize the memory and computation, thus effectively avoid the huge time and energy overhead caused by data moving between memory and computation units. However, the memristive stateful logic still faces the reliability challenges caused by the variability of memristor, which prevents it from practical applications. A reliability reinforcement method with low overhead in delay, area and peripheral circuits is thus needed to be studied urgently. This paper proposes a novel method of reliability reinforcement based on logic gates' margin. By optimizing circuit structure and driving voltage configuration, the margin of logic gates is improved to tolerant memristors' variability to the maximum extent, and thus reinforces logic gates' reliability. Simulations demonstrate that the proposed method can improve the allowed threshold variability range by 42% and 92% for 2-input NAND gate and 2-input OR gate, respectively. Benchmark with other methods shows that the proposed margin-based reinforcement method achieves almost the same reliability reinforcement effect, but the overhead in area and peripheral circuit is greatly reduced.

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A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Cited by 13 publications

References 42 publications

Crossbar-Compatible Stateful Logic Using Phase Change Memory

Crossbar-Compatible Stateful Logic Using Phase Change Memory

Stateful Logic Using Phase Change Memory

Margin‐based reliability reinforcement method for stateful logic

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