A charge-oriented model for MOS transistor capacitances

Ward, D.E.; Dutton, R.W.

doi:10.1109/jssc.1978.1051123

Cited by 356 publications

(52 citation statements)

References 2 publications

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“…We have recently [2], [3] investigated linear dynamic models of the MOSFET using the classic figures of merit U , , , and U,,, [4]. One point that we found particularly striking and disturbing was that the models of Meyer [5], Ward and Dutton [6], and Paulos and Antoniadis [7] all predict that U , , and U,,, diverge to infinity as the MOS-FET approaches saturation [3]. Moreover, this divergence occurs even if a series resistance is added to the gate terminal or if a multisection (i.e., distributed) MOSFET model is used.…”

Section: Mosfet Capacitance and Conductance In The Saturation Regimementioning

confidence: 99%

MOSFET capacitance and conductance in the saturation regime

Glasser

1991

IEEE Electron Device Lett.

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The relationship between capacitance and conductance of a MOSFET is examined in the region where velocity saturation dominates. In this domain it is shown that charge on the drain terminal (physically distinct from that in the channel) must be considered in order to keep the model from predicting the unphysical result that C,, is negative. It is also shown that, under the same assumptions, g, < C g g / 7 where g, is the transconductance, 7 is the transit time, and Cgg is the gate capacitance. Fig. 1. An n-channel MOSFET biased in saturation. The carriers are traveling at saturated velocity in the region from x,, to L .ECAUSE of its industrial importance, MOSFET capaci-B tance research has been the object of intense theoretical and experimental scrutiny for the last 25 years. The earliest work might be characterized as an attempt to develop rigorous three-terminal linear models by simplifying the results of distributed R C transmission line analyses. More recent work has had a number of foci, but the principle issue has been one of finding models suitable for large-signal circuit simulation. Thus we have seen investigations of charge conservation issues, generalizations to include the body terminal, results produced by device simulation, measurements on short-channe1 devices, and so on. Tsividis presents an extensive bibliography in [l]. Most of this work, though by no means all, has focused on the nonsaturation regime. Nevertheless, for analog circuit design and much of digital circuit design, when signals are being processed, MOSFET transistors are generally operated in saturation. By and large, the assumption used in analytical investigations has been that Cgd = Cd, = 0 for the intrinsic MOSFET in saturation. We have recently [2], [3] investigated linear dynamic models of the MOSFET using the classic figures of merit U , , , and U,,,[4]. One point that we found particularly striking and disturbing was that the models of Meyer [5], Ward and Dutton [6], and Paulos and Antoniadis [7] all predict that U , , and U,,, diverge to infinity as the MOS-FET approaches saturation [3]. Moreover, this divergence occurs even if a series resistance is added to the gate terminal or if a multisection (i.e., distributed) MOSFET model is used. The reason for this unphysical prediction is that all of these models predict that the impedance seen looking into the drain terminal at saturation is infinite.Clearly the output conductance of a MOSFET is not zero. There are, of course, extrinsic resistive parasitics such as the resistance of diffised active area (e.g., n+), contact resisManuscript received April 1, 1991; revised June 12, 1991. The author is with the Electronic Systems Technology Office, Defense IEEE Log Number 9102734. Advanced Projects Agency, Arlington, VA 22209.tance, and lightly doped drains. Since these effects are in series with the transistor's output conductance, they cannot be responsible for turning a zero output conductance into a nonzero output conductance. Moreover, while we would expect that extrinsic parasit...

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Section: Mosfet Capacitance and Conductance In The Saturation Regimementioning

confidence: 99%

MOSFET capacitance and conductance in the saturation regime

Glasser

1991

IEEE Electron Device Lett.

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“…The expressions for the terminal charges were derived using the Ward-Dutton linear charge-partition method [38] …”

Section: Differential Capacitance Modelmentioning

confidence: 99%

“…where f 0 is the applied frequency in a.c. device simulation and H 21 in (37) corresponds only to intrinsic transistor and Y parameters in (38) are for extrinsic transistor which includes parasitic resistance R g , R s and R i . The total (intrinsic + extrinsic) gate-to-source (C gs ) and gate-to-drain (C gd ) capacitances without considering overlap capacitances are calculated as…”

Section: Rf Performance Investigationsmentioning

confidence: 99%

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Sarkar

De²,

Dey

et al. 2012

J Comput Electron

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We report a systematic, quantitative investigation of analog and RF performance of cylindrical surroundinggate (SRG) silicon MOSFET. To derive the model, a pseudotwo-dimensional (2-D) approach applying Gauss's law in the channel region is extended for the cylindrical SRG MOSFET. Based on surface potential approach, expressions of drain current and differential capacitances are obtained analytically. Analog/RF figures of merit of SRG MOSFET are studied, including transconductance efficiency g m /I d , intrinsic gain, output resistance, cutoff frequency f T , maximum oscillation frequency f max and gain bandwidth product GBW. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modeled predictions have been extensively compared with the simulated characteristics obtained from the ATLAS device simulator and a nice agreement is observed with a wide range of geometrical parameters.

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“…Alternatively, the nonlinear currents due to the intrinsic charge flow may be described by the time derivative of charge functions reflecting the charge stored in the four terminals gate, drain, source and bulk at a given time point [13]. A circuit model for this approach is given in Fig.…”

Section: The Charge-oriented Approachmentioning

confidence: 99%

Modelling and simulating charge sensitive mos circuits

Günther¹,

Denk²,

Feldmann³

1996

Mathematical Modelling of Systems

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We show how charge distribution effects in MOS transistors are reflected only correctly by models based on the physical properties of the device. Hence one has to consider carefully the impact of modelling to obtain correct results for MOS circuits by numerical simulation. Additionally, the choice of an appropriate integration scheme is essential for both reliable and efficient simulation results. To spotlight these influences, we use a charge pump as an instructive test circuit and discuss a variety of modelling approaches.

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A charge-oriented model for MOS transistor capacitances

Cited by 356 publications

References 2 publications

MOSFET capacitance and conductance in the saturation regime

MOSFET capacitance and conductance in the saturation regime

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Modelling and simulating charge sensitive mos circuits

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