A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

Sun, Lei; Li, Bing; Wong, Anson; Ng, Wai Tung; Pun, Kong Pang

doi:10.1109/tcsi.2014.2363517

Cited by 40 publications

(14 citation statements)

References 25 publications

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“…With a supply voltage fluctuation of 50 mV pp , the proposed design has a similar SNDR to other designs. We noted that the power consumption of the ADC core reported in references [ 5 , 6 , 7 , 8 ] do not consider the reference-voltage regulator. Hence, for fair comparison, we provided the estimated power consumed in these reference-voltage regulators in Table 1 .…”

Section: Measurement Resultsmentioning

confidence: 99%

“… * STP stands for self-timed pre-charging. ** Power consumption of reference-voltage regulators needed in references [ 5 , 6 , 7 , 8 ] are estimated based on the regulator used in reference [ 4 ] with the assumption that they have the same regulator FOM reg defined in reference [ 10 ] and the same dropout voltage. …”

Section: Figurementioning

confidence: 99%

“…Even with advanced rectifiers, such as the reconfigurable resonant regulating rectifier (R 3 rectifier), the ripple of the rectified voltage can still be measured in tens of mV [ 1 ]. For conventional SAR ADCs adopted in such systems [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [ 2 , 3 , 4 ].…”

Section: Introductionmentioning

confidence: 99%

“…In the past, most designs focused on optimizing the power and area of the sub-blocks in the SAR ADC core [ 5 , 6 , 7 , 8 ], while only a few studies aimed to optimize the reference-voltage regulator [ 2 , 3 , 4 , 11 ]. It was found that if the power consumption of the reference-voltage regulator is included, the FOM of ADC degrades from 100 fJ/c-s to 1000 fJ/c-s [ 2 ] or from 25 fJ/c-s to 738 fJ/c-s [ 3 ].…”

Section: Introductionmentioning

confidence: 99%

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A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Yang

Zhou

Liu

et al. 2018

Sensors

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This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal–oxide–semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mVpp and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Yang

Zhou

Liu

et al. 2018

Sensors

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show abstract

“…Thus, reducing DAC switching power is recently a crucial topic to improve the overall power efficiency. Several low-power DAC switching techniques have been published including energy saving [1], charge recycling switching (CRS) [2], input range prediction (IRP) [3], charge average switching (CAS) [4], charge recycling with LSB-down [5], set-and-down [6], merge-and-split (MS) [7], bidirectional single-side (BSS) [8], Manuscript V cm -based [9], and one-side switching instead (OSSI)+higherbit switching instead (HBSI) [10] to reduce the switching energy by 69%, 71%, 74%, 75%, 77%, 81%, 83%, 86%, 88%, and 97%, respectively, compared with the conventional approach [6]. The switching power can also be reduced by detecting the input range and skipping unnecessary switching.…”

Section: Introductionmentioning

confidence: 99%

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Lee

Lin

Hsieh

2016

IEEE Trans. Circuits Syst. I

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This paper presents a low-voltage and powerefficient 10 bit successive-approximation register (SAR) analogto-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a timedomain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm 2 . At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signalto-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3 µW to 2.5 µW and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.Index Terms-Low power, low voltage, SAR ADC.

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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

Jin

Guo

et al. 2021

Circuits Syst Signal Process

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A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

Cited by 40 publications

References 25 publications

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

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