A Class AB Amplifier for LCD Driver

Ito, Ryoko; Itakura, Tetsuro; Minamizaki, Hironori

doi:10.1109/vlsic.2007.4342693

Cited by 19 publications

(22 citation statements)

References 2 publications

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“…Yu et al [15] proposed a class-B output buffer for flat-panel-display column driver, for which a comparator was used in the negative feedback path to eliminate the quiescent current in the output stage. Kim et al [6] proposed a multi-level multi-phase charge-recycling method for low-power AMLCD column drivers.…”

Section: Introductionmentioning

confidence: 99%

“…The author proposed this charge-recycling method to reduce the power consumption incurred in driving highly capacitive column lines by storing the charge into the external capacitors and reusing it in the next cycle. Itakura et al [13][14][15][16][17][18][19][20] proposed an output amplifier in which the phase compensation is achieved by introducing a zero, which is formed by the load capacitance and the phase compensation resistor connected between the output of the amplifier and the capacitive load.…”

Section: Introductionmentioning

confidence: 99%

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Low Offset and High Slew Rate Buffer amplifier for LCD Application

Mishra¹,

Raikwar²

2015

IJCA

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The proposed buffer achieves low offset and high slew rate in proposed circuit NMOS folded cascode operation amplifier is used instead of rail to rail operation amplifier, use of only NMOS folded cascode operation amplifier reduces the number of MOS used in circuit and using auto zero negative feedback will provide full swing for positive and negative feedback polarity pixel, and to decrease the offset a current distributed load is used which increases DC gain of operational amplifier and as DC gain increases it reduces offset voltage and increases slew rate with same bias current used in folded and summing stage of operational amplifier. The proposed circuit is simulated and verified in LT-spice and Microwind simulation tool using 350nm CMOS TSMC foundry with 3.3 V supply voltage the offset calculated is around .2mV and slew rate is 14V/µs.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Offset and High Slew Rate Buffer amplifier for LCD Application

Mishra¹,

Raikwar²

2015

IJCA

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“…The column drivers of an LCD driving system hold the most significant role in achieving fast speed capabilities, high resolution and low power dissipation, as they distribute the pixel information into the display active matrix. Among the core building blocks of which an LCD column driver is composed, the output buffer amplifiers mainly determine the speed, resolution, voltage swing and power consumption of the whole driver [1][2][3][4][5][6][7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, as a high open-loop gain is required to obtain a low-valued systematic offset voltage, a two-stage amplifier architecture is traditionally adopted in the LCD driver [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. Since the additional Miller capacitance required for frequency compensation would involve a sensible silicon area consumption, most recently proposed amplifiers achieve stability by exploiting dominant-pole compensation at the high-capacitive-impedance output node.…”

Section: Introductionmentioning

confidence: 99%

“…However, to provide fast driving capabilities to the output stage, a few additional current comparators are commonly included in the basic two-stage amplifier topology, in order to improve large-signal performance by sensing the rising and falling edges of the input waveform and switch on additional driving transistors [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. Nevertheless, although the current comparators allow to enhance the output amplifier slew-rate, a current mismatch is required to turn off the output devices during quiescent operation.…”

Section: Introductionmentioning

confidence: 99%

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Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control

Marano

Palumbo

Pennisi

2010

Analog Integr Circ Sig Process

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The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a railto-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push-pull output sections of two basic complementary-type input amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary biasing network integrated in the input differential stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-ls settling time under a 3-V full voltage swing, while drawing only 3.5-lA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations.

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A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

Tsai

Wang

2011

Analog Integr Circ Sig Process

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The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push-pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 lm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 lW, with settling times of 0.7 and 0.68 ls for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 9 48 lm 2 .

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A Class AB Amplifier for LCD Driver

Cited by 19 publications

References 2 publications

Low Offset and High Slew Rate Buffer amplifier for LCD Application

Low Offset and High Slew Rate Buffer amplifier for LCD Application

Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control

A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

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