A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot

Elhebeary, Mahmoud; Yang, Chih-Kong Ken

doi:10.1109/tcsi.2020.3006777

Cited by 7 publications

(3 citation statements)

References 23 publications

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“…Despite the shortcomings highlighted above, the advantage of loop stability has encouraged other reported works to propose and refine FVF architectures. Among the circuit techniques that have been developed are mirrored control [60]- [62], adaptive and dynamic biasing [34], [63], adaptive and dynamic compensation [23], [25], super source follower (SSF) buffers [24], [30], [36], [64], and Class D with multilevel pulse width modulation (MLPWM) gate control [31]. These techniques aim to provide the necessary fast response to the load current transient improving load regulation while maintaining high current efficiency.…”

Section: A Flipped Voltage Follower Aldosmentioning

confidence: 99%

“…In contrast to the control methods described above, Class D MLPWM gate driving is employed in [31] to drive the FVF-LDO. To control the gate of the pass transistor, a feedforward transition-detection path (FFTDP) is incorporated to enhance the switching at high loads, from 0 to 300 mA.…”

Section: A Flipped Voltage Follower Aldosmentioning

confidence: 99%

“…As mentioned in [44], the settling time, TRC, and the voltage droop during the load transient affect the overall accuracy. Hence, the settling time, TRC, is a key parameter of an OCL-ALDO [31], [47], [56], and is more important than the response time, TRS [50], evidently shown in Fig. 5.…”

Section: A Benchmarking State-of-the-art Aldosmentioning

confidence: 99%

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Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review

et al. 2022

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Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-theart architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.INDEX TERMS Linear low-dropout regulators (LDOs), power management integrated circuits (PMICs), analog LDOs (ALDO), capacitor-less output, adaptive biasing, bulk modulation, power supply rejection (PSR), flipped voltage follower (FVF), charge pump.

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