A CMOS 10 Gb/s clock and data recovery circuit with a novel adjustable K/sub pd/ phase detector

Chen, Xinyu; Green, M.M.

doi:10.1109/iscas.2004.1329000

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

DOI: 10.1109/iscas.2004.1329000

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A CMOS 10 Gb/s clock and data recovery circuit with a novel adjustable K/sub pd/ phase detector

Xinyu Chen

M.M. Green

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A new current-integrating bang-bang phase detector for clock and data recovery

Yuan

2008

2008 51st Midwest Symposium on Circuits and Systems

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This paper proposes a new current-integrating bang-bang phase detector that is insensitive to data transient disturbances. The phase detector extracts early-late phase information between the input and retimed data by integrating the input data and its complementary on two identical capacitors. In addition, it employs only one regenerative DFF for phase detection, significantly lowering hardware cost. The phase detector has been implemented in TSMC-0.18µm 1.8V CMOS technology and analyzed using Spectre-RF from Cadence Design Systems with BSIM3.3v device models. Simulation results are presented.

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A new current-integrating bang-bang phase detector for clock and data recovery

Yuan

2008

2008 51st Midwest Symposium on Circuits and Systems

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show abstract

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A CMOS 10 Gb/s clock and data recovery circuit with a novel adjustable K/sub pd/ phase detector

Cited by 1 publication

References 5 publications

A new current-integrating bang-bang phase detector for clock and data recovery

A new current-integrating bang-bang phase detector for clock and data recovery

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