A CMOS area image sensor with pixel-level A/D conversion

Fowler, Boyd; Gamal, Abbas El; Yang, David

doi:10.1109/isscc.1994.344659

Cited by 97 publications

(50 citation statements)

References 5 publications

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“…In previous works, decimation was performed at the chip level [7], [8]. But this entails a high bit rate at the pixel output, which limits the bit resolution, frame rate, and window size.…”

Section: Decimator Designmentioning

confidence: 99%

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Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Mahmoodi

Joseph

2008

2008 51st Midwest Symposium on Circuits and Systems

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Abstract-Area and power optimization of a first-order deltasigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a verticallyintegrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed inside the pixel to decrease its output bit rate. The proposed ADC has an area of 32 × 31 µm 2 and consumes 680 nW of power to achieve 80 dB of signal-to-noise ratio with a frame rate of 50 Hz. The circuit was implemented in 0.18 µm CMOS technology with a die area of 2 mm 2 and has been sent for fabrication.I. INTRODUCTION Dynamic range (DR) and signal-to-noise ratio (SNR) are two major specifications of CMOS image sensors [1]. High DR and SNR are demanded by several applications. Linear sensors achieve a high SNR by photocurrent integration but have a low DR. While the human eye has a DR of over 100 dB, linear sensors capture only 70 dB without saturation. Time-based linear sensors have a higher DR but need a long integration time, which limits the frame rate [2]. Logarithmic sensors employ a transistor in subthreshold mode to convert the photodiode current in logarithmic scale to a voltage to achieve a DR of over 160 dB [3]. However, these sensors suffer from high fixed-pattern noise (FPN) and low SNR. It has been shown that FPN can be effectively reduced using a calibration method [3]. Hence, having low SNR remains as the main drawback. A delta-sigma analog-to-digital converter (ADC) for pixel-level data conversion can achieve high SNR to improve the SNR of logarithmic sensors.Pixel-level data conversion has several advantages. Digital pixels can reduce the readout noise to achieve a higher SNR. Also, since the ADCs are working at very low speed in the subthreshold region, they consume very low power. In addition, the readout speed is not as limited by bus capacitance so higher frame rates may be possible. The main issue with digital pixels is the large pixel size [1].In [4], different pixel designs for high DR and SNR have been compared. The authors conclude that with the present methods, if not impossible, it would be difficult to achieve high DR and SNR with a reasonable pixel size. But recent interest in vertically-integrated image sensors means more area will be available inside the pixel to process the sensitive signal of the photodiode [4], [5]. In [5], an image sensor has been designed for infrared applications using vertical integration. While its

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“…In previous works, decimation was performed at the chip level [7], [8]. But this entails a high bit rate at the pixel output, which limits the bit resolution, frame rate, and window size.…”

Section: Decimator Designmentioning

confidence: 99%

“…The first implementation of a delta-sigma pixel was reported by Fowler et al [7]. The main issue with their work was a high output bit rate, since decimation was done outside the pixel.…”

mentioning

confidence: 99%

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Mahmoodi

Joseph

2008

2008 51st Midwest Symposium on Circuits and Systems

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“…The maximum resolution of the ADC is determined by the gain of the comparator, and the speed of the ADC is determined by both the gain and the bandwidth of the comparator. Assuming subthreshold operation" and that the early voltage and gate efficiency of all the transistors are the same, it can be shown that the gain of the comparator is approximately AV=() (6) where Veariy 5 the early voltage of the transistors, i is the gate efficiency of the transistors, and is the thermal voltage. Again using the same assumptions, it can be shown that the gain bandwidth of the comparator is approximately GBW= 'bzas , (7) 8ir---output where 'bias 5 the tail current of the differential pair, and is the output capacitance of the comparator.…”

Section: Mcbs Adcmentioning

confidence: 99%

<title>Techniques for pixel-level analog-to-digital conversion</title>

1998

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Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an oversampling technique which uses a one bit first order Ez modulator for each 2 x 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi-channel--bit-serial (MCBS) ADC. The technique uses successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible and JR imagers. From the comparison it appears that the L\ ADC is better suited to JR imagers, while the MCBS ADC is better suited to imagers in the visible range.

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“…In the mid-1970's, infrared focal plane arrays (IRFPAs) began to be developed for infrared imaging in military and astronomical applications [37,38]. A typical IRFPA consists of a detector array fabricated with a narrow bandgap semiconductor (nominal bandgap values of 0.25 eV to 0.1 eV) connected to a so-called silicon multiplexer.…”

Section: Photon Counting Hybrid Pixel Detectorsmentioning

confidence: 99%

“…In an integrating imaging system there is a clear separation between the time used to collect the charge resulting from the photon interactions and the time when this accumulated charge is read from the pixels and processed. This feature is exploited in both column-level [35,36] and pixel-level [37,38,39,40,41,42,43] ADCs to operate, respectively, all columns or all pixels in parallel. As a result, slower ADCs than those in the chip-level approach can be used.…”

Section: Pixel-level Analog-to-digital Convertersmentioning

confidence: 99%

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

Bello¹

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A CMOS area image sensor with pixel-level A/D conversion

Cited by 97 publications

References 5 publications

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

<title>Techniques for pixel-level analog-to-digital conversion</title>

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

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